A 256-channel multi-phase clock sampling-based time-to-digital converter implemented in a Kintex-7 FPGA

Abstract

One of the advantages using a multi-phase clock embedded in field programmable gate arrays (FPGAs) to construct a time-to-digital converter (TDC) is its great multi-channel capability. However, many technical aspects limit the time resolution that can be achieved in the TDC architecture. In this paper, a series of solutions to these technical challenges are proposed and a 256-channel TDC with a reasonably high performance is implemented in a single chip of Xilinx Kintex-7 FPGA. The test results show that the time resolution of dualchannel measurements is in the range of 27.1 ps ∼ 56.2 ps with a very low sensitivity to ambient temperature. The measurement dead time is three system clock cycles, namely 4.3 ns, which means the peak measurement throughput of the TDC can reach 233 M events per second. The improved performance will make TDCs with the architecture more applicable for varieties of applications.