A 16 mW 250 ps Double-Hit-Resolution Input-Sampled Time-to-Digital Converter in 45-nm CMOS

Abstract

Several new approaches for multi-hit delay-line-based time-to-digital converters (TDCs) are discussed and an input-sampled TDC architecture is realized in 45-nm SOI CMOS. The TDC is characterized by applying a pseudo-random-bit-sequence as an input signal, which consists of multiple time-events/hits. Each low or high transition inside the binary input represents a time-event to be recorded. As the time-event carrying input travels through the delay-line, it generates its delayed phases, which are then sampled by a reference clock with period equal to the delay of the delay-line. The resulting sampled digital word contains a snapshot of all the time-events occurring within one clock period. The TDC achieves a time-resolution of 25 ps and the continuous sampling of the delay-line allows this unique architecture to achieve ideally unlimited dynamic-range. The prototype circuit dissipates 16 mW of power, occupies silicon area of 0.36 mm2, and is capable of detecting two consecutive time-events/transitions at a distance of 250 ps, which is the best double-hit-resolution reported in literature for any TDC.