Throughput Architecture Research Articles

Active Queue Management in L4S with Asynchronous Advantage Actor-Critic: A FreeBSD Networking Stack Perspective

Bufferbloat is one of the leading causes of high data transmission latency and jitter on the Internet, which severely impacts the performance of low-latency interactive applications such as online streaming, cloud-based gaming/applications, Internet of Things (IoT) applications, voice over IP (VoIP), real-time video conferencing, and so forth. There is currently a pressing need for developing Transmission Control Protocol (TCP) congestion control algorithms and bottleneck queue management schemes that can collaboratively control/reduce end-to-end latency, thus ensuring optimal quality of service (QoS) and quality of experience (QoE) for users. This paper introduces a novel solution by experimentally integrate the low latency, low loss, and scalable throughput (L4S) architecture (specified by the IETF in RFC 9330) in FreeBSD framework with the asynchronous advantage actor-critic (A3C) reinforcement learning algorithm. The first phase involves incorporating a modified dual-queue coupled active queue management (AQM) system for L4S into the FreeBSD networking stack, enhancing queue management and mitigating latency and packet loss. The second phase employs A3C to adjust and fine-tune the system performance dynamically. Finally, we evaluate the proposed solution’s effectiveness through comprehensive experiments, comparing it with traditional AQM-based systems. This paper contributes to the advancement of machine learning (ML) for transport protocol research in the field. The experimental implementation and results presented in this paper are made available through our GitHub repositories.

Design and performance analysis of manchester coder-based body channel communication using FPGA

In general, the Body Channel Communication (BCC) is used to transmit human physiological signals over vast distances. Also, the Error-correcting codes can detect and rectify faults in long-range data transmission. Data is encoded in a predetermined manner for secure transmission. In this paper, a Manchester encoding-based high throughput architecture is proposed for a body channel communication system with a low-power operation mode. Further, the Manchester encoder is designed for high throughput performance with a low complexity architecture, and an analog front-end processing circuit which includes two stage pre-amplifiers. Also, the transmission rate on the BCC transceiver side is boosted by the maximum Consecutive Identical Digit (CID), which is limited by Manchester codes. The Manchester code format is generated by encoding the sensed data. Additionally, a full gain buffer is used to reduce data loss and hardware overhead. Results demonstrate that the suggested Manchester encoder is implemented in 90 nano meter (nm) technology, and the 10 Megabits per second (Mbps) data rate is obtained with a configurable operating frequency ranging from 1 to 100 Megahertz (MHz).

High-Throughput Hardware Design for Linear Equation System Solving of VVC Affine Prediction

The affine prediction is the main novelty in the inter-frame prediction of Versatile Video Coding (VVC) standard. However, implementing the affine prediction requires a huge computational effort that makes mandatory the use of dedicated hardware accelerators to achieve real-time processing and meet the constraints of area and power dissipation for mobile devices. In light of this, this work presents different approaches for a hardware design dedicated to solving the linear equation system, which is essential for refiningthe affine Motion Vector. Synthesis results show that the High- Throughput architecture, which explores the parallelism of internal operations, can reach an accuracy of 99.99%, requiring 333.9kgates to be implemented and presenting a power dissipation of 120.4mW when running at 540MHz, the operational frequency required to process 60 frames per second of HD 1080p videos.

Heterogeneous microstructures tuned in a high throughput architecture

A new method applied to the sensor proposed by Zhang et al. in 2018 is demonstrated in this paper that combines the benefits of this design with the fast heating possible with nanocalorimetry. By applying a PID regulated pulse instead of a constant wattage, we unlock an accessible method to sense morphological changes occurring over short time periods that would be invisible to methods based only on heat capacity. In this study, multilayer Ni/Al thin films were linearly heated at 25, 50, 100, and 200 K/s to over 700°C, showing two distinct peaks in resistance change with activation energies of 55±4 and 74±7 kJ/mol, respectively. Through Scanning Transmission Electron Microscopy (STEM) and Energy Dispersive X-ray Analysis (EDX) analysis on cross sections taken ex situ from samples quenched before and after the peaks of interest, we find strong evidence that peak 1 corresponds to Ni diffusing through Al grain boundaries forming intermetallic phases that essentially block the highly conductive Al pathway. This presents the potential to design and calibrate novel heterogeneous structures in a high throughput manner.

Secure image encryption using high throughput architectures of PRINT cipher for radio frequency identification applications

With the enhancement of technology, data security has become incredibly significant. Nowadays, images and vital information are used in real-time, and high throughput architecture is required for internet of things and real-time applications. We mainly focus on the high throughput architecture of PRINT cipher. PRINT cipher is a lightweight block cipher with a block size of 48-bit and 96-bit. Loop-unrolled, 48-bit pipelined, and 96-bit pipelined architectures are designed and implemented on different field programmable gate array and application-specific integrated circuit platforms. The maximum operating frequency obtained for 48-bit pipelined is 259.67 MHz on Virtex-4 and 310.67 MHz for 96-bit pipelined on Virtex-5. Finally, with the help of a controller, 48-bit high throughput pipelined architecture was utilized for image encryption of both grayscale and color images. The security analysis of encrypted images for color and grayscale images using PRINT cipher shows better performance and more robust protection against statistical, entropy, and differential attacks.

High throughput architecture for multiscale variational optical flow

High throughput architecture for multiscale variational optical flow

Heterogeneous Microstructures Tuned in a High Throughput Architecture

Heterogeneous Microstructures Tuned in a High Throughput Architecture

Two Distributed Arithmetic Based High Throughput Architectures of Non-Pipelined LMS Adaptive Filters

Distributed arithmetic (DA) is an efficient look-up table (LUT) based approach. The throughput of DA based implementation is limited by the LUT size. This paper presents two high-throughput architectures (Type I and II) of non-pipelined DA based least-mean-square (LMS) adaptive filters (ADFs) using two’s complement (TC) and offset-binary coding (OBC) respectively. We formulate the LMS algorithm using the steepest descent approach with possible extension to its power-normalized LMS version and followed by its convergence properties. The coefficient update equation of LMS algorithm is then transformed via TC DA and OBC DA to design and develop non-pipelined architectures of ADFs. The proposed structures employ the LUT pre-decomposition technique to increase the throughput performance. It enables the same mapping scheme for concurrent update of the decomposed LUTs. An efficient fixed-point quantization model for the evaluation of proposed structures from a realistic point-of-view is also presented. It is found that Type II structure provides higher throughput than Type I structure at the expense of slow convergence rate with almost the same steady-state mean square error. Unlike existing non-pipelined LMS ADFs, the proposed structures offer very high throughput performance, especially with large order DA base units. Furthermore, they are capable of performing less number of additions in every filter cycle. Based on the simulation results, it is found that 256^th order filter with 8^th order DA base unit using Type I structure provides 9.41× higher throughput while Type II structure provides 16.68× higher throughput as compared to the best existing design. Synthesis results show that 32^nd order filter with 8^th order DA base unit using Type I structure achieves 38.76% less minimum sampling period (MSP), occupies 28.62% more area, consumes 67.18% more power, utilizes 49.06% more slice LUTs and 3.31% more flip-flops (FFs), whereas Type II structure achieves 51.25% less MSP, occupies 21.42% more area, consumes 47.84% more power, utilizes 29.10% more slice LUTs and 1.47% fewer FFs as compared to the best existing design.

Enhanced parallel CFAR architecture with sharing resources using FPGA

The real time CFAR processor needs a very high computational performance. To meet with the real-time requirements, this paper presents an implementation of a new hardware parallel design using ACOSD-CFAR detector. The aim of this work is to increase the architecture throughput and decrease the power consumption while maintaining a high resolution target detection. Our proposed implementation exploits the properties of the ACOSD-CFAR detector to enhance it with a parallel architecture include some sharing resources. Compared to conventional implementation of CFAR, the proposed architecture increases the throughput from 2,576 Mbit/s to 4,736 Mbit/s by 184% and reduces the power consumption by 15%. The design is implemented on a Zync 7000 FPGA board, which is considered as a common validation platform.

GPU-based power converter transient simulation with matrix exponential integration and memory management

With the extensive application of power electronic equipment in power systems, electromagnetic transient (EMT) simulation involving power converters becomes more challenging. Due to its multithreads and high throughput architecture, the graphics processing unit (GPU) can be used to accelerate those EMT simulations. A GPU-based matrix exponential method and its memory management for power converter transient simulation are proposed in this paper. A parallel exponential integration algorithm is established from two aspects to fully utilize the GPU multithreads capability. The matrix exponentials which are recomputed with the on/off state changes of power electronic switches are cached in GPU memory. The simulation efficiency is improved by reusing the cached data and reducing heterogeneous data transmission between CPU and GPU. Several strategies are experimented to manage the cache memory considering the EMT simulation workflow. The proposed memory management expands the simulation capability by substantially reducing the memory requirement and maintains the speed advantage of the GPU-based simulator. The proposed method is tested on wind power plants of different scales with power electronic interfaced wind generators. Simulation results indicate that the proposed method and its memory management expand the simulation capability and achieve speedups.

Validating the Sharing Behavior and Latency Characteristics of the L4S Architecture

The strict low-latency requirements of applications such as virtual reality, online gaming, etc., can not be satisfied by the current Internet. This is due to the characteristics of classic TCP such as Reno and TCP Cubic which induce high queuing delays when used for capacity-seeking traffic, which in turn results in unpredictable latency. The Low Latency, Low Loss, Scalable throughput (L4S) architecture addresses this problem by combining scalable congestion controls such as DCTCP and TCP Prague with early congestion signaling from the network. It defines a Dual Queue Coupled (DQC) AQM that isolates low-latency traffic from the queuing delay of classic traffic while ensuring the safe co-existence of scalable and classic flows on the global Internet. In this paper, we benchmark the DualPI2 scheduler, a reference implementation of DQC AQM, to validate some of the experimental result(s) reported in the previous works that demonstrate the co-existence of scalable and classic congestion controls and its low-latency service. Our results validate the co-existence of scalable and classic flows using DualPI2 Single queue (SingleQ) AQM, and queue latency isolation of scalable flows using DualPI2 Dual queue (DualQ) AQM. However, the rate or window fairness between DCTCP without fair-queuing (FQ) pacing and TCP Cubic using DualPI2 DualQ AQM deviates from the original results. We attribute the difference in our results and the original results to the sensitivity of the L4S architecture to traffic bursts and the burst sending pattern of the Linux kernel.

Performance Analysis of High Throughput MAP Decoder for Turbo Codes and Self Concatenated Convolutional Codes

The effect of parallelism on Bit Error Rate (BER) performance of Turbo Code (TC) and Self Concatenated Convolutional Code (SECCC) with different levels of parallelism and frame sizes is investigated. Next Iteration Initialization (NII) method is employed for mitigating the BER degradation resulting from increased parallelism. In order to analyze and compare the architectural performance of both schemes, this paper presents the Very High Speed Integrated Circuit Hardware Description Language (VHDL) design of Maximum Aposteriori Probability (MAP) decoder for TC and SECCC, both employing the same constituent code. The simulation results show that for BER of 10−4, without parallelism, TC is 0.4 dB superior to SECCC, whereas, with parallelism of 64, the difference in performance between both schemes reduces to 0.25 dB. It is found that SECCC outperforms TC for frame sizes less than or equal to 2048 bits, when invoking a parallelism of 16, 32 and 64. The BER performance of both schemes shows that SECCC outperforms TC at parallelism of 256 by 0.3 dB at BER of 10−4. Hence, for high throughput architectures employing higher parallelism (beyond 64 and 128) without significant degradation in BER performance, SECCC performs better than TC. The synthesis results of VHDL design of the MAP decoder obtained using Xilinx ISE verify that both schemes have equal clock frequency and resource consumption. It is demonstrated that the MAP decoder achieves the clock frequency of 86.3 MHz which is capable of producing a throughput of 691 Mbps using parallelism of 64.

Software-Directed Techniques for Improved GPU Register File Utilization

Throughput architectures such as GPUs require substantial hardware resources to hold the state of a massive number of simultaneously executing threads. While GPU register files are already enormous, reaching capacities of 256KB per streaming multiprocessor (SM), we find that nearly half of real-world applications we examined are register-bound and would benefit from a larger register file to enable more concurrent threads. This article seeks to increase the thread occupancy and improve performance of these register-bound applications by making more efficient use of the existing register file capacity. Our first technique eagerly deallocates register resources during execution. We show that releasing register resources based on value liveness as proposed in prior states of the art leads to unreliable performance and undue design complexity. To address these deficiencies, our article presents a novel compiler-driven approach that identifies and exploits last use of a register name (instead of the value contained within) to eagerly release register resources. Furthermore, while previous works have leveraged “scalar” and “narrow” operand properties of a program for various optimizations, their impact on thread occupancy has been relatively unexplored. Our article evaluates the effectiveness of these techniques in improving thread occupancy and demonstrates that while any one approach may fail to free very many registers, together they synergistically free enough registers to launch additional parallel work. An in-depth evaluation on a large suite of applications shows that just our early register technique outperforms previous work on dynamic register allocation, and together these approaches, on average, provide 12% performance speedup (23% higher thread occupancy) on register bound applications not already saturating other GPU resources.

An In-Memory VLSI Architecture for Convolutional Neural Networks

This paper presents an energy-efficient and high throughput architecture for convolutional neural networks (CNN). Architectural and circuit techniques are proposed to address the dominant energy and delay costs associated with data movement in CNNs. The proposed architecture employs a deep in-memory architecture, to embed energy-efficient low swing mixed-signal computations in the periphery of the SRAM bitcell array. An efficient data access pattern and a mixed-signal multiplier are proposed to exploit data reuse opportunities in convolution. Silicon-validated energy, delay, and behavioral models of the proposed architecture are developed and employed to perform large-scale system simulations. System-level simulations using these models show 97% detection accuracy on the MNIST data set, along with 4.9× and 2.4× improvements in energy efficiency and throughput, respectively, leading to 11.9× reduction in energy-delay product as compared with a conventional (SRAM + digital processor) architecture.

GPU NTC Process Variation Compensation With Voltage Stacking

Near-threshold computing (NTC) has the potential to significantly improve efficiency in high throughput architectures, such as general-purpose computing on graphic processing unit (GPGPU). Nevertheless, NTC is more sensitive to process variation (PV) as it complicates power delivery. We propose GPU stacking, a novel method based on voltage stacking, to manage the effects of PV and improve the power delivery simultaneously. To evaluate our methodology, we first explore the design space of GPGPUs in the NTC to find a suitable baseline configuration and then apply GPU stacking to mitigate the effects of PV. When comparing with an equivalent NTC GPGPU without PV management, we achieve 37% more performance on average. When considering high production volume, our approach shifts all the chips closer to the nominal non-PV case, delivering on average (across chips) ${\approx} 80$ % of the performance of nominal NTC GPGPU, whereas when not using our technique, chips would have ${\approx} 50$ % of the nominal performance. We also show that our approach can be applied on top of multifrequency domain designs, improving the overall performance.

High throughput FPGA Implementation of Advanced Encryption Standard Algorithm

The growth of computer systems and electronic communications and transactions has meant that the need for effective security and reliability of data communication, processing and storage is more important than ever. In this context, cryptography is a high priority research area in engineering. The Advanced Encryption Standard (AES) is a symmetric-key criptographic algorithm for protecting sensitive information and is one of the most widely secure and used algorithm today. High-throughput, low power and compactness have always been topic of interest for implementing this type of algorithm. In this paper, we are interested on the development of high throughput architecture and implementation of AES algorithm, using the least amount of hardware possible. We have adopted a pipeline approach in order to reduce the critical path and achieve competitive performances in terms of throughput and efficiency. This approach is effectively tested on the AES S-Box substitution. The latter is a complex transformation and the key point to improve architecture performances. Considering the high delay and hardware required for this transformation, we proposed 7-stage pipelined S-box by using composite field in order to deal with the critical path and the occupied area resources. In addition, efficient AES key expansion architecture suitable for our proposed pipelined AES is presented. The implementation had been successfully done on Virtex-5 XC5VLX85 and Virtex-6 XC6VLX75T Field Programmable Gate Array (FPGA) devices using Xilinx ISE v14.7. Our AES design achieved a data encryption rate of 108.69 Gbps and used only 6361 slices ressource. Compared to the best previous work, this implementation improves data throughput by 5.6% and reduces the used slices to 77.69%.

High throughput resource shared 2D integer transform computation for H.264/MPEG-4 AVC

Two dimensional (2D) integer transforms are used in all the profiles of H.264/MPEG-4 Advanced Video Coding (AVC) standard. This paper presents a resource shared architecture of 2D 4×4 and 8×8 integer transforms in H.264/MPEG-4 AVC coders. Existing architectures use separate designs to compute 2D 4×4 and 8×8 forward/inverse integer transform. Shared resource architectures for 4×4 and 8×8 transforms can be used to reduce the implementation area without sacrificing high throughput. Matrix decomposition is used to show that the 2D 4×4 forward/inverse integer transform of two independent data blocks can be obtained from one 2D 8×8 forward/inverse integer transform circuit. A high throughput architecture is used as the base design for the implementation of 2D 8×8 forward/inverse transform. Data rearrangement stages are added to the base design to compute the 2D 4×4 forward/inverse transform. The proposed dual-clock pipelined architecture does not require any transpose memory. As compared to existing designs, the proposed design operates on two independent 4×4 sub-blocks. Hence, the overall throughput of the 2D 4×4 forward/inverse transform computation increases by approximately 200% with less than a 5% increase in the gate count. The proposed design operates at a clock frequency of approximately 1.25 GHz and achieves a throughput of 7 G and 18.7 G pixels/sec for each block of 4×4 and 8×8 forward integer transforms, respectively. Due to resource shared implementation and high throughput, the proposed design can be used for real-time H.264/MPEG-4 AVC processing.

VLSI Implementation of a Rate Decoder for Structural LDPC Channel Codes

This paper proposes a low complexity low-density parity check decoder (LDPC) design. The design mainly accomplishes a message passing algorithm and systolic high throughput architecture. The typical mathematical calculations are based on the observation that nodes with high log likelihood ratio provide almost same information in every iteration and can be considered as stationary, we propose an algorithm in which the parity check matrix H is updated to a reduced complexity form every time a stationary node is encountered which results in lesser number of numerical computations in subsequent iterations. In this paper, we contemplately focuses on computational complexity and the decoder design significantly benefits from the high throughput point of view and the various improvisations introduced at various levels of abstraction in the decoder design. Threshold Controlled Min Sum Algorithm implements the LDPC decoder design for a code compliant with wired and wireless applications. A high performance LDPC decoder has been designed that achieves a throughput of 0.890 Gbps. The whole design of LDPC Decoder is designed, simulated and synthesized using Xilinx ISE 13.1 EDA Tool.

A high throughput architecture for a low complexity soft-output demapping algorithm

Abstract. Iterative channel decoders such as Turbo-Code and LDPC decoders show exceptional performance and therefore they are a part of many wireless communication receivers nowadays. These decoders require a soft input, i.e., the logarithmic likelihood ratio (LLR) of the received bits with a typical quantization of 4 to 6 bits. For computing the LLR values from a received complex symbol, a soft demapper is employed in the receiver. The implementation cost of traditional soft-output demapping methods is relatively large in high order modulation systems, and therefore low complexity demapping algorithms are indispensable in low power receivers. In the presence of multiple wireless communication standards where each standard defines multiple modulation schemes, there is a need to have an efficient demapper architecture covering all the flexibility requirements of these standards. Another challenge associated with hardware implementation of the demapper is to achieve a very high throughput in double iterative systems, for instance, MIMO and Code-Aided Synchronization. In this paper, we present a comprehensive communication and hardware performance evaluation of low complexity soft-output demapping algorithms to select the best algorithm for implementation. The main goal of this work is to design a high throughput, flexible, and area efficient architecture. We describe architectures to execute the investigated algorithms. We implement these architectures on a FPGA device to evaluate their hardware performance. The work has resulted in a hardware architecture based on the figured out best low complexity algorithm delivering a high throughput of 166 Msymbols/second for Gray mapped 16-QAM modulation on Virtex-5. This efficient architecture occupies only 127 slice registers, 248 slice LUTs and 2 DSP48Es.

Network-Level FPGA Acceleration of Low Latency Market Data Feed Arbitration

Financial exchanges provide market data feeds to update their members about changes in the market. Feed messages are often used in time-critical automated trading applications, and two identical feeds (A and B feeds) are provided in order to reduce message loss. A key challenge is to support A/B line arbitration efficiently to compensate for missing packets, while offering flexibility for various operational modes such as prioritising for low latency or for high data reliability. This paper presents a reconfigurable acceleration approach for A/B arbitration operating at the network level, capable of supporting any messaging protocol. Two modes of operation are provided simultaneously: one prioritising low latency, and one prioritising high reliability with three dynamically configurable windowing methods. We also present a model for message feed processing latencies that is useful for evaluating scalability in future applications. We outline a new low latency, high throughput architecture and demonstrate a cycle-accurate testing framework to measure the actual latency of packets within the FPGA. We implement and compare the performance of the NASDAQ TotalView-ITCH, OPRA and ARCA market data feed protocols using a Xilinx Virtex-6 FPGA. For high reliability messages we achieve latencies of 42ns for TotalView-ITCH and 36.75ns for OPRA and ARCA. 6ns and 5.25ns are obtained for low latency messages. The most resource intensive protocol, TotalView-ITCH, is also implemented in a Xilinx Virtex-5 FPGA within a network interface card; it is used to validate our approach with real market data. We offer latencies 10 times lower than an FPGA-based commercial design and 4.1 times lower than the hardware-accelerated IBM PowerEN processor, with throughputs more than double the required 10Gbps line rate.