High-Throughput Hardware Design for Linear Equation System Solving of VVC Affine Prediction

Abstract

The affine prediction is the main novelty in the inter-frame prediction of Versatile Video Coding (VVC) standard. However, implementing the affine prediction requires a huge computational effort that makes mandatory the use of dedicated hardware accelerators to achieve real-time processing and meet the constraints of area and power dissipation for mobile devices. In light of this, this work presents different approaches for a hardware design dedicated to solving the linear equation system, which is essential for refiningthe affine Motion Vector. Synthesis results show that the High- Throughput architecture, which explores the parallelism of internal operations, can reach an accuracy of 99.99%, requiring 333.9kgates to be implemented and presenting a power dissipation of 120.4mW when running at 540MHz, the operational frequency required to process 60 frames per second of HD 1080p videos.