Abstract
The real time CFAR processor needs a very high computational performance. To meet with the real-time requirements, this paper presents an implementation of a new hardware parallel design using ACOSD-CFAR detector. The aim of this work is to increase the architecture throughput and decrease the power consumption while maintaining a high resolution target detection. Our proposed implementation exploits the properties of the ACOSD-CFAR detector to enhance it with a parallel architecture include some sharing resources. Compared to conventional implementation of CFAR, the proposed architecture increases the throughput from 2,576 Mbit/s to 4,736 Mbit/s by 184% and reduces the power consumption by 15%. The design is implemented on a Zync 7000 FPGA board, which is considered as a common validation platform.
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