Abstract

The effect of parallelism on Bit Error Rate (BER) performance of Turbo Code (TC) and Self Concatenated Convolutional Code (SECCC) with different levels of parallelism and frame sizes is investigated. Next Iteration Initialization (NII) method is employed for mitigating the BER degradation resulting from increased parallelism. In order to analyze and compare the architectural performance of both schemes, this paper presents the Very High Speed Integrated Circuit Hardware Description Language (VHDL) design of Maximum Aposteriori Probability (MAP) decoder for TC and SECCC, both employing the same constituent code. The simulation results show that for BER of 10−4, without parallelism, TC is 0.4 dB superior to SECCC, whereas, with parallelism of 64, the difference in performance between both schemes reduces to 0.25 dB. It is found that SECCC outperforms TC for frame sizes less than or equal to 2048 bits, when invoking a parallelism of 16, 32 and 64. The BER performance of both schemes shows that SECCC outperforms TC at parallelism of 256 by 0.3 dB at BER of 10−4. Hence, for high throughput architectures employing higher parallelism (beyond 64 and 128) without significant degradation in BER performance, SECCC performs better than TC. The synthesis results of VHDL design of the MAP decoder obtained using Xilinx ISE verify that both schemes have equal clock frequency and resource consumption. It is demonstrated that the MAP decoder achieves the clock frequency of 86.3 MHz which is capable of producing a throughput of 691 Mbps using parallelism of 64.

Highlights

  • Turbo Codes (TCs) were introduced in 1993 by Berrou [1]. They are Parallel Concatenated Convolutional Codes (PCCC) [2] which belong to Forward Error Correcting (FEC) codes. They are able to operate near Shannon’s capacity limit [3] and employed to support a variety of communication standards such as 3rd Generation Partnership Project Long Term Evolution (3GPP LTE), IEEE Standard P802.16 known as Worldwide interoperability for Microwave Access (WiMAX), Global System for Mobile communications (GSM), Universal Mobile Telecommunication System (UMTS), and Digital Video Broadcastingsatellite Services to Handheld (DVB-SH) [4]

  • As the Self Concatenated Convolutional Code (SECCC) scheme with parallelism does not already exist in literature, so for comparing its performance we develop the TC scheme with the same RSC code and code rate and show that SECCC scheme has a significant improvement in Bit Error Ratio (BER) performance compared to TC scheme, for shorter frames (≤ 2048-bits) with higher parallelism (≥ 16)

  • Decoder, the VHDL design of the Maximum Aposteriori Probability (MAP) decoder discussed in Section III is configured for TC and SECCC and synthesized by using Xilinx ISE for Virtex-6 FPGA (XCVLX240T)

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Summary

INTRODUCTION

Turbo Codes (TCs) were introduced in 1993 by Berrou [1]. They are Parallel Concatenated Convolutional Codes (PCCC) [2] which belong to Forward Error Correcting (FEC) codes. It tends to increase throughput and reduce latency Based on this algorithm, the implementation of a fully parallel turbo decoder was presented in [18]. Turbo decoder for achieving throughput of 100 Gbps is presented in [22] for higher code rates. A parallel turbo decoder architecture, which covers full range of code rates and provides higher throughput gains and better hardware efficiency, is presented in [23]. The aspect that the BER performance of error correction codes decreases at higher parallelism is an important consideration for design implementation in high throughput scenarios. Through synthesis of this configurable MAP decoder, it is shown that TC and SECCC schemes exhibit the same architectural performance.

ENCODING AND DECODING OF TC AND SECCC
DECODING
ARCHITECTURE OF THE MAP DECODER
ARCHITECTURE OF PARALLEL MAP DECODER
RESULTS AND DISCUSSIONS
ERROR RATE PERFORMANCE
CONCLUSION AND FUTURE WORK
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