Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding

Abstract

Maximum a posteriori probability (MAP) decoder is an integral part of the most exciting error correcting turbo decoders. A high speed architecture for MAP decoder is an essential entity for the design of high throughput turbo decoder which is widely used in the recent wireless communication standards. In this paper, a new sliding window approach for the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm used in the design of MAP decoder is presented. An architecture for MAP decoder based on this approach and its operation is also included in this paper. The proposed MAP decoder architecture is implemented on field programmable gate array (FPGA) and the results are discussed. The proposed MAP decoder operates at a maximum frequency of 346 MHz and is compared with the state of the art implementations of MAP decoder. Finally, the bit error rate (BER) performance of an implemented MAP decoder in a communication environment is measured.