Through-wafer Interconnects Research Articles

High density and through wafer copper interconnections and solder bumps for MEMS wafer-level packaging

This paper proposes an innovative process combining the electroforming of high-density and through-wafer copper interconnections and solder bumps for advanced MEMS packaging. Vias with the diameter of 30 to 100 μm were etched through on a 4-inch and 550 μm-thick silicon substrate by ICP-DRIE process for an aspect ratio up to 18.3. MRTV1 silicon rubber layer was employed for substrates quickly releasing after copper-interconnections electroforming. Compared to the tedious wet etching or mechanical polishing process, this peel-off relasing process provides a simpler way. After another lithography process, mushroom shape eutecic solder bumps (63Sn/37Pb) were directly electroformed on the top of each copper interconnection with the height of 100 μm, and reflowed at 200 °C for 5 min to form solder spheres. The feasibility of making highly dense and uniform electrical interconncetions has been successfully demonstrated on the wafer with fabricated micro temperature sensors. The estimated resistance for the copper-column of different diameters are characterized lower than 13.1 mΩ and this process provides a bump density up to 9648 interconnects/cm2.

Through-wafer interconnect technology for silicon

This paper presents a novel method for creating through-wafer interconnects via an anisotropically etched groove in a (100)-silicon wafer. The idea is based on the realization of interconnection lines on the inclined sidewalls of the anisotropically etched grooves, which transfer the metalization to the back side of the wafer without open through-holes. The process itself is compatible with standard semiconductor technology and can be applied at the wafer level resulting in low packaging costs. All post interconnect processes are developed independently and can be added to any IC fabrication process. They are performed at the back side of the wafer at the packaging step, so during this processing the front side of the wafer can be protected from scratches and pollution. The key feature of the method presented is the coating of the anisotropically etched grooves with a polyimide and an electrodeposited photoresist. Further, methods to improve the photoresist uniformity over three-dimensional structures are discussed. Copper interconnects have been realized to show the feasibility of this through-wafer technique for front-to-back electrical interconnections. The thickness of the copper interconnects has been increased by copper electroplating to reduce their electrical resistance further and to increase their mechanical strength.

Cantilever-Type Microelectromechanical Systems Probe Card with Through-Wafer Interconnects for Fine Pitch and High-Speed Testing

A new microelectromechanical systems (MEMS) probe card made of electroplated nickel cantilevers, which has compliant structure, with through-wafer interconnections for IC testing is developed. The measured contact resistance was less than 0.5 ohm and leakage current was approximately 0.13 nA between tips and pads. In addition, planarity of tips and the alignment of x- and y-axes were satisfied with conventional needle probe card performance. Therefore, this probe card is suitable for wafer-level burn-in testing and function testing of memory and RF devices. In particular, since through-wafer interconnection can offer the shortest signal line path and reduce signal delay, it is possible to implement fine pitch and high-speed devices. The probe was fabricated with the 4-inch silicon substrate.

Advanced processing techniques for through-wafer interconnects

The fabrication of interconnects used in future microelectronic devices and for three-dimensional (3D) integration of these components will require advanced integrated circuit (IC) processing techniques. One attractive approach to providing increased connectivity is to use through-wafer interconnects. The primary challenge to implementing 3D stacking is the formation of these high aspect ratio interconnects with a sufficiently small diameter and, consequently, with sufficiently high density. Processing techniques to fabricate through-wafer interconnects in silicon for applications that require multichip stacking or contacts on both sides of the wafer will be described. The techniques used for fabrication of the vertical interconnects are compatible with complementary metal–oxide–semiconductor technology and executed within the thermal budget of a completed IC. The processing techniques to be described include: deep silicon etching (DRIE) to form small diameter vias, insulator lining, adhesion/barrier layer deposition, seed layer deposition, copper electroplating, and chemical mechanical planarization of copper. Through-wafer copper interconnects have been formed with via diameters of 50–100 μm on 4 and 6 in. silicon wafers containing no active devices and at temperatures no greater than 200 °C.

Fabrication of multi-pixel TES microcalorimeters with an electrodeposited Sn absorber and Bi absorber

We have developed multi-pixel TES microcalorimeters in order to realize high-energy resolution and X-ray imaging. A Sn absorber and a Bi absorber were formed on Si3N4 and SiO2 membrane using two-step exposure photolithography and electrodeposition. A FEM analysis was carried out to investigate the performance of the X-ray microabsorbers. In addition, a superconducting through-wafer interconnection was demonstrated considering the future X-ray imager using microcalorimeters. Detail of the fabrication techniques, characteristics and simulation results of two types of the microabsorbers, as well as those of the calorimeters are described.

Igniters and temperature sensors for a micro-scale combustion system

Abstract This paper presents the development of micro-fabricated “on-chip” polysilicon igniters and temperature sensors for the combustion system of a micro-gas turbine engine. We have reported the design and fabrication results of a novel through-wafer interconnect scheme that could greatly facilitate electrical contacts in multi-level MEMS devices by allowing direct electrical access to the backside of a wafer. This paper presents the results of a further effort that uses these interconnects to make electrical contacts to a thin-film polysilicon resistor so as to evaluate its ignition capability and its use as a wall temperature sensor for the micro-gas turbine engine. An application of the through-wafer interconnects to a concept demonstration of thin-film polysilicon resistive igniters for the micro-engine showed that it was possible to initiate combustion and locally raise the temperature of the igniter to 900 °C so long as the chip is thermally isolated. The results were found to be in good agreement with the predictions of an FEM thermal model. The possibility of using the resistors as temperature sensors is also examined. The non-linear variation of polysilicon resistivity with annealing temperatures due to complex effects resulting from dopant atom segregation, secondary grain growth and crystallographic relaxation reduced the operating range of the sensors to 450 °C.

Process compatible polysilicon-based electrical through-wafer interconnects in silicon substrates

Electrical through-wafer interconnects (ETWI) which connect devices between both sides of a substrate are critical components for microelectromechanical systems (MEMS) and integrated circuits (IC), as they enable three-dimensional (3-D) structures and permit new packaging and integration geometries. Previously demonstrated ETWI are very difficult to integrate with standard semiconductor fabrication processes, not compatible with released sensors, do not permit extensive processing on both sides of the wafer, and are in general very application specific. This work describes the design, fabrication, and characterization of an ETWI technology for silicon substrates that can be broadly integrated with MEMS and IC processes. This interconnect is a passively isolated electrical through-wafer polysilicon plug, with a 20 /spl mu/m diameter, 10-14 /spl Omega/ resistance, and less than 1 pF capacitance. Plasma etching from both sides of the wafer is used to achieve a high-aspect ratio via (20:1 through 400 /spl mu/m). The process is compatible with standard lithography, standard wafer handling, subsequent high-temperature processing, and released sensors integration. N-type and p-type versions are demonstrated, and isolated ground planes are added to provide shielding against substrate noise. Electrical properties of these ETWI are measured and analytically modeled. These ETWI are appropriate for integration with devices with impedances much greater than the ETWI, such as piezoresistive and capacitive sensor arrays.

Multiple Through-wafer Interconnects for MEMS Applications

This chapter reports on the design and manufacturing of multiple through-wafer interconnects for stacking of microelectromechanical devices. The feedthroughs have been applied to an interconnect (intermediate) layer for an integrated microphone. The integrated microphone consists of the transducer part and an application specific integrated circuit (ASIC). The two parts are joined by stacking them on top of each other with the interconnect (intermediate) layer between them. The intermediate layer is a multifunctional layer. It provides the microphone with an acoustic frontchamber. The intermediate layer ensures the interchange of acoustical and electrical signals with the environment. Also, the intermediate layer protects the microphone during dicing, chip handling and in operation. The two active components are electrically connected through the intermediate layer by multiple wafer frontside to backside interconnects. The feedthrough interconnects are provided with under bump metallizations (UBM), solder bumps and sealing rings on the microphone side and top surface metallizations (TSM) on the ASIC side. The entire metallization system is based on electroplating techniques. The patterning of the metallizations has been done utilizing an electrodepositable photoresist (EDPR) as a plating mold. Several EDPR processes have been developed which are optimized for the respective metallization. The feedthrough interconnects have been optimized in terms of series resistance and parallel capacitance. Electrical characterization of the feedthrough interconnects has been carried out analytically and experimentally. The series resistance of one single interconnect wire is in the order of 100 mΩ. The parallel (parasitic) capacitance is in the order of 2 pF. Coupling between two adjacent feedthrough interconnects is negligible for low relative humidity ( 90%) the impedance between two wires may be reduced due to a condensed water film. Sensitivity measurements performed before and after bonding of the interconnect layer to the microphone showed identical results which proves sufficient (TΩ) isolation between the feedthrough wires.

Through-wafer electrical interconnect for multilevel microelectromechanical system devices

This article reports the design, fabrication, and experimental demonstration of through-wafer interconnects capable of allowing direct electrical access to the interior of a multilevel microelectromechanical system device. The interconnects exploit the ability to conformally coat a high aspect ratio trench with a thick layer of tetraethylorthosilicate to isolate a through-wafer silicon plug that can provide electrical contact across two sides of a low resistivity wafer. They hold the potential of a tenfold reduction in the parasitic capacitance of previously reported through-wafer vias, and are shown to make reliable contacts to the back side of a polysilicon resistive element. The high temperature capability of the interconnects is also examined, however, their application is found to be limited to temperatures below 1000 °C due to localized degradation near the isolating trenches.

Integration of through-wafer interconnects with a two-dimensional cantilever array

High-density through-wafer interconnects are incorporated in a two-dimensional (2D) micromachined cantilever array. The design addresses alignment and density issues associated with 2D arrays. Each cantilever has piezoresistive deflection sensors and high-aspect ratio silicon tips. The fabrication process and array operation are described. The integration of cantilevers, tips, and interconnects enables operation of a high-density 2D scanning probe array over large areas.

Challenges in plasma etching and patterning for fabrication of new systems and devices

Besides plasma etching of through-wafer interconnects in wafer stacks for vertical integration of chips [M. Engelhardt et al., Proceedings of the 23rd Annual Tegal Plasma Seminar (1997)] fabrication of Pt storage nodes with nontapered sidewalls is one of the most challenging tasks of plasma process technology today. In this work the fabrication of vertical Pt profiles was achieved by plasma processing with resist mask. In this novel approach, the buildup of thin redepositions of Pt onto the sidewalls of the resist, obtained as a result of processing in pure Ar plasmas, is utilized to achieve a sidewall steepness of the patterned Pt film which is determined by the steepness of the preetch resist profile. After pattern transfer and resist stripping, the portion of the redepositions protruding above the fabricated storage node was completely removed by chemical mechanical polishing.

Modern Applications of Plasma Etching and Patterning in Silicon Process Technology

Besides plasma etching of through-wafer interconnects in wafer stacks for vertical integration of chips, fabrication of platinum (Pt) electrodes with non-tapered sidewalls for the storage node in modern memories (DRAMs and FeRAMs) is one of the most challenging tasks of plasma process technology today. This paper describes the achievement of vertical integration of chips by plasma etching of high aspect ratio interchip vias. The etching processes for dielectrics, single crystal silicon, and the organic glue layer were all optimized for minimum reactive ion etching (RIE) lag i.e. for minimum decrease of etch rate with increasing etch depth. Furthermore the fabrication of perfect Pt electrodes for modern DRAMs and FeRAMs is reported. Vertical Pt profiles were achieved by plasma processing with resist mask. In this novel approach, the build-up of thin redepositions of Pt onto the sidewalls of the resist, obtained as a result of processing in pure Ar plasmas, is utilized to achieve a sidewall steepness of the patterned Pt film which is determined by the steepness of the pre-etch resist profile. After pattern transfer and resist stripping, the portion of the redepositions protruding above the fabricated storage node was completely removed by chemical mechanical polishing.

The offset cube: a three-dimensional multicomputer network topology using through-wafer optics

Three-dimensional packaging technologies are critical for enabling ultra-compact, massively parallel processors (MPPs) for embedded applications. Through-water optical interconnect has been proposed as a useful technology for building ultra-compact MPPs since it provides a simplified mechanism for interconnecting stacked multichip substrates. This paper presents the offset cube, a new network topology designed to exploit the packaging benefits of through-wafer optical interconnect in ultra-compact MPP systems. We validate the offset cube's topological efficiency by developing deadlock-free adaptive routing protocols with modest virtual channel requirements (only two virtual channels per link needed for full adaptivity). A preliminary analysis of router complexity suggests these protocols can be efficiently implemented in hardware. We also present a 3D mesh embedding for the offset cube. Network simulations show the offset cube performs comparably to a bidirectional 3D mesh of equal size under uniform, hot-spot, and trace-driven traffic loads. While the offset cube is not proposed as a general replacement for the mesh topology it leverages the benefits of through-wafer optical interconnect more effectively than a mesh by completely eliminating chip-to-chip wires for data signals. Hence, the offset cube is an effective topology for interconnecting ultra-compact MCM-level MPP systems.

A three-dimensional high-throughput architecture using through-wafer optical interconnect

This paper presents a three-dimensional, highly parallel, optically interconnected system to process high-throughput stream data such as images. The vertical optical interconnections are realized using. Integrated optoelectronic devices operating at wavelengths to which silicon is transparent. These through-wafer optical signals are used to vertically optically interconnect stacked silicon circuits. The thin film optoelectronic devices are bonded directly to the stacked layers of silicon circuitry to realize self-contained vertical optical interconnections. Each integrated circuit layer contains analog interface circuitry, namely, detector amplifier and emitter driver circuitry, and digital circuitry for the network and/or processor, all of which are fabricated using a standard silicon integrated circuit foundry. These silicon circuits are post processed to integrate the thin film optoelectronics using standard, low cost, high yield microfabrication techniques. The three-dimensionally integrated architectures described herein are a network and a processor. The network has been designed to meet off-chip I/O using a new offset cube topology coupled with naming and renting schemes. The performance of this network is comparable to that of a three-dimensional mesh. The processing architecture has been defined to minimize overhead for basic parallel operations. The system goal for this research is to develop an integrated processing node for high-throughput, low-memory applications.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Low-temperature silicon wafer-to-wafer bonding using gold at eutectic temperature

Abstract Micromechanical smart sensor and actuator systems of high complexity become commercially viable when realized as a multi-wafer device in which the mechanical functions are distributed over different wafers and one of the wafers is dedicated to contain the readout circuits. The individually-processed wafers can be assembled using wafer-to-wafer bonding and can be combined to one single functional electro-mechanical unit using through-wafer interconnect, provided that the processes involved comply with the constraints imposed by the proper operation of the active electrical and micromechanical subsystems. This implies low-temperature wafer-to-wafer bonding and through-wafer interconnect. Au/Si eutectic bonding has been investigated as it can conveniently be combined with bulk-micromachined through-wafer interconnect. The temperature control in eutectic bonding has been shown to be critical.

Fresnel phase plate lenses for through-wafer optical interconnections

While the advantages of optical over electrical interconnects for conventional 2-D VLSI and wafer-scaleintegrated (WSI) circuits have not been clearly demonstrated, for 3-D interconnection structures such as those necessary for stacked wafer and similar architectures, the trade-off between using optical or electrical methods for vertical links is not straightforward. Current work on fabricating a through-wafer optical interconnect within a hybrid-WSI environment is motivated by the need to obtain experimental data on the overall performance of an optical interconnect so that this trade-off can be clarified inthe case of hybrid-WSI and in the general case at least more well defined. This paper details the design and fabrication of SiO(2) Fresnel phase plate lens arrays for use in the experimental 1.3-microm wavelength through-wafer optical interconnects to be constructed. These 0.8-N.A. lenses have submicron minimum linewidths and are VLSI process compatible. Preliminary results are presented indicating that, with the use of these lens arrays, vertical optical interconnect densities comparable with that of on chip bonding pads ( approximately 250-microm pitch) are obtainable within these architectures.

On the feasibility of through-wafer optical interconnects for hybrid wafer-scale-integrated architectures

The desire to achieve a high degree of parallelism in multiwafer wafer-scale-integrated (WSI) based architectures has stimulated study of three-dimensional interconnect structures obtained by stacking wafer circuit boards and providing interconnections vertically between wafers over the entire wafer area in addition to planar connections. While the advantages of optical over electrical interconnects for conventional two-dimensional VLSI and wafer-scale-integrated circuits have not been clearly demonstrated, for dense multiwafer WSI or hybrid-WSI three-dimensional architectures, the ability to pass information optically between circuit planes without mechanical electrical contacts offers potential advantages. While optical waveguides are readily fabricated in the wafer plane, waveguiding vertically through the wafer is difficult. If additional processing is required for waveguides or lenses, it should be compatible with standard VLSI processing. This paper presents one method of meeting this criterion. Using optical devices operating at wavelengths beyond the Si absorption cutoff, low-loss through-wafer propagation between WSI circuit planes can be achieved over the distances of interest (≈ 1 mm) with the interstitial Si wafers as part of the interconnect "free-space" transmission medium. The thickness of existing VLSI layers can be readily adjusted in featureless regions of the wafer to provide antireflection windows such that >90 percent transmittance can be obtained through p-type silicon. Initial results show a 400-percent source-detector coupling enhancement is obtainable for these optical interconnections using VLSI process-compatible SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> phase-reversal zone plate lenses.

Production Contact Via Etching for GaAs MMICs.

ABSTRACTResearch has been undertaken in several major research laboratories to achieve a commercially successful GaAs via hole etching process. This work presents the achievement of results with the desired characteristics for through-wafer GaAs interconnects or vias, for production of MMICs.We report vias acceptable for use in the production of microwave GaAs field effect transistors fabricated by a reactive ion etching process. Using conventional resist masks and non toxic gases, aspect ratios of up to 10:1 have been achieved with via sizes as small as 40μm × 40μm. Typical wafer thicknesses were greater than 100μm and the process showed high selectivity to the frontside metallization. The etching conditions had to be varied as a function of overall substrate area and exposed GaAs. To determine optimum process parameters, the RF power and resultant DC bias; gas flow rates and ratios; and system pressure were systematically varied. The effects of changes in area of wafer to be etched and of the composition of the electrode material were also studied. Details are presented of the optimum etching parameters for use in 2″ and 3″ GaAs MMIC production.