Through-wafer interconnect technology for silicon

Abstract

This paper presents a novel method for creating through-wafer interconnects via an anisotropically etched groove in a (100)-silicon wafer. The idea is based on the realization of interconnection lines on the inclined sidewalls of the anisotropically etched grooves, which transfer the metalization to the back side of the wafer without open through-holes. The process itself is compatible with standard semiconductor technology and can be applied at the wafer level resulting in low packaging costs. All post interconnect processes are developed independently and can be added to any IC fabrication process. They are performed at the back side of the wafer at the packaging step, so during this processing the front side of the wafer can be protected from scratches and pollution. The key feature of the method presented is the coating of the anisotropically etched grooves with a polyimide and an electrodeposited photoresist. Further, methods to improve the photoresist uniformity over three-dimensional structures are discussed. Copper interconnects have been realized to show the feasibility of this through-wafer technique for front-to-back electrical interconnections. The thickness of the copper interconnects has been increased by copper electroplating to reduce their electrical resistance further and to increase their mechanical strength.