Through Silicon Via Research Articles

Employing Thermal Oxidation and Through-Silicon Via Technologies in CuO-Based Sensors for Room-Temperature NO2 Detection

We present the development and characterization of room-temperature CuO gas sensor fabricated through a thermal oxidation process complemented by a through-silicon via (TSV) structure. The TSV structure is a tapered hole with the top width measuring approximately 190 um and narrowing to 103 um at the bottom. The CuO film serves as the sensing material, with its predominant (111) orientation confirmed through X-ray diffraction analysis. Transmission electron microscopy analysis indicated lattice spacing of 0.23 nm within the CuO samples, corresponding to the (111) plane. Sensor performance was evaluated at a room temperature of 25 °C, showing response rates of 19.3%, 34.6%, 39.3%, and 46.3% to NO2 concentrations of 0.5, 1, 2, and 5 ppm, respectively. Stability testing of the sensor at 1 ppm NO2 concentration across five cycles demonstrated a consistent response around 34.6% with a deviation of less than 2%. The CuO material exhibited enhanced selectivity for NO2 over other gases such as NH3, CO2, CO, H2, H2S, and SO2.

Recent Progress of TGV Technology for High Performance Semiconductor Packaging

In recent semiconductor packaging, the adoption of through silicon via (TSV) technology has become crucial for the integration of 2.5 and 3D Si chips, and interposers. The TSV offers significant advantages including high interconnect density, shortened signal pathways, and improved electrical performance. However, challenges such as electrical loss, substrate warpage, and high manufacturing costs are associated with TSV implementation. In contrast, glass-based through-glass vias (TGVs) exhibit promising characteristics such as excellent insulation properties, cost-effectiveness, and variable coefficient of thermal expansion (CTE) values that mitigate warpage in stacked devices. Moreover, they facilitate miniaturization and support high-frequency applications. This paper provides an overview of recent advancements in glass substrate, TGV drilling techniques, functional layer depositions, and Cu-filling processes in semiconductor packaging evolution.

A novel plating bath device for reducing surface copper thickness and improving wafer-scale uniformity

Through silicon via (TSV) technology plays a pivotal role in three-dimensional integrated circuits. However, excessive surface thickness and uneven wafer plating during TSV copper electroplating pose significant challenges to TSV reliability. This paper proposes a novel rotating cathode electroplating technique that utilizes flow field induction by a rotating cathode to significantly reduce the surface copper thickness by approximately 8 μm, leading to improved uniformity of wafer-scale electroplating and facilitating rapid TSV filling. This study focuses on the impact of cathode rotation speed and chip position on TSV filling quality. The experimental findings demonstrate that increasing the cathode rotation speed reduces the diffusion layer thickness, thereby enhancing filling quality. Additionally, variations in chip position influence surface copper thickness. The introduction of bis(3-sulfopropyl) disulfide accelerant expedites the filling process, boosts the filling ratio, and enables defect-free TSV filling. This study offers valuable insights into the wafer-scale TSV electroplating process and facilitates the optimization of parameter settings during electroplating.

A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM.

A multi-layer stacked Dynamic Random Access Memory (DRAM) platform is introduced to address the memory wall issue. This platform features high-density vertical interconnects established between DRAM units for high-capacity memory and logic units for computation, utilizing Wafer-on-Wafer (WoW) hybrid bonding and mini Through-Silicon Via (TSV) technologies. This 3DIC architecture includes commercial DRAM, logic, and 3DIC manufacturing processes. Their design documents typically come from different foundries, presenting challenges for signal integrity design and analysis. This paper establishes a lumped circuit based on 3DIC physical structure and calculates all values of the lumped elements in the circuit model with the transmission line model. A Cross-Process Signal Integrity Analysis (CPSIA) method is introduced, which integrates three different manufacturing processes by modeling vertical stacking cells and connecting DRAM and logic netlists in one simulation environment. In combination with the dedicated buffer driving method, the CPSIA method is used to analyze 3DIC impacts. Simulation results show that the timing uncertainty introduced by 3DIC crosstalk ranges from 31 ps to 62 ps. This analysis result explains the stable slight variation in the maximum frequency observed in vertically stacked memory arrays from different DRAM layers in the physical testing results, demonstrating the effectiveness of this CPSIA method.

Through-polymer, via technology-enabled, flexible, lightweight, and integrated devices for implantable neural probes

In implantable electrophysiological recording systems, the headstage typically comprises neural probes that interface with brain tissue and integrated circuit chips for signal processing. While advancements in MEMS and CMOS technology have significantly improved these components, their interconnection still relies on conventional printed circuit boards and sophisticated adapters. This conventional approach adds considerable weight and volume to the package, especially for high channel count systems. To address this issue, we developed a through-polymer via (TPV) method inspired by the through-silicon via (TSV) technique in advanced three-dimensional packaging. This innovation enables the vertical integration of flexible probes, amplifier chips, and PCBs, realizing a flexible, lightweight, and integrated device (FLID). The total weight of the FLIDis only 25% that of its conventional counterparts relying on adapters, which significantly increased the activity levels of animals wearing the FLIDs to nearly match the levels of control animals without implants. Furthermore, by incorporating a platinum-iridium alloy as the top layer material for electrical contact, the FLID realizes exceptional electrical performance, enabling in vivo measurements of both local field potentials and individual neuron action potentials. These findings showcase the potential of FLIDs in scaling up implantable neural recording systems and mark a significant advancement in the field of neurotechnology.

Study on the design and fabrication of Silicon-Based integrated current sensor based on 3D Through-Silicon-Via (TSV) Rogowski coil

With the rapid advancement of microelectronics, 3D silicon-based integration microsystem technology has found widespread applications in various interconnected domains such as power generation, electric vehicles, smart grids, automation, and the Internet of Things (IoT). The high integration density within three-dimensional integrated microsystems has resulted in increasingly complex coupling between components, underscoring the critical importance of system health diagnostics. Presently, current waveform analysis, which yields valuable insights into the circuit system's condition, serves as a prevalent technique for system health assessment. However, traditional current sensors, typically packaged as discrete devices for current sensing, are inadequate for internal electrical signal detection within 3D IC microsystems. Therefore, this paper presents the design of a silicon-based integrated 3D Through-Silicon-Via (TSV) Rogowski coil tailored for in-situ electric current measurement. The structure and parasitic parameters of the 3D TSV Rogowski coil are meticulously determined through finite element method (FEM) simulations, facilitating the development of an appropriate signal processing circuit. Moreover, an Ordinary Differential Equation (ODE) current reconstruction method is proposed for measuring current. Leveraging this structural and circuit design, on-chip silicon-based integrated 3D TSV Rogowski coils are fabricated, followed by rigorous experimental validation. The experimental results convincingly attest to the effective in-situ current measurement capability of the on-chip silicon-based integrated 3D TSV Rogowski coil for 3D IC microsystems.

Low Stress TSV Arrays for High-Density Interconnection

In three-dimensional (3D) stacking, the thermal stress of through-silicon via (TSV) has a significant influence on chip performance and reliability, and this problem is exacerbated in high-density TSV arrays. In this study, a novel hollow tungsten TSV (W–TSV) is presented and developed. The hollow structure provides space for the release of thermal stress. Simulation results showed that the hollow W–TSV structure can release 60.3% of thermal stress within the top 2 μm from the surface, and thermal stress can be decreased to less than 20 MPa in the radial area of 3 μm. The ultra-high-density (1600 TSV∙mm−2) TSV array with a size of 640 × 512, a pitch of 25 μm, and an aspect ratio of 20.3 was fabricated, and the test results demonstrated that the proposed TSV has excellent electrical and reliability performances. The average resistance of the TSV was 1.21 Ω. The leakage current was 643 pA and the breakdown voltage was greater than 100 V. The resistance change is less than 2% after 100 temperature cycles from −40 to 125 °C. Raman spectroscopy showed that the maximum stress on the wafer surface caused by the hollow W–TSV was 31.02 MPa, which means that there was no keep-out zone (KOZ) caused by the TSV array. These results indicate that this structure has great potential for applications in large-array photodetectors and 3D integrated circuits.

Thermal-Mechanical Property of High Aspect Ratio TSV in Advanced IC integration and Packaging

Advanced packaging of integrated circuits (IC) plays a critical role on the way towards high performance, high density, low power consumption and light weight of electronics. Through-silicon vias (TSV) is the heart of 3D IC integration and packaging. However, copper protrusion due to mismatch of coefficients of thermal expansion (CTE) between copper and silicon, which may result in the dielectric material breakdown, becomes the bottleneck of TSV in high-temperature application. In this paper, thermal-mechanical property of high aspect ratio TSV is investigated through experiments under different annealing process, which will help to accelerate the widely application of TSV in advanced packaging of electronics in the future.

Multimodal machine learning for predicting heat transfer characteristics in micro-pin fin heat sinks

As three-dimensional integrated circuit (3D-IC) chip technology advances, thermal management has become increasingly important because of increasing heat flux from thermal stacking. Micro-pin fin-embedded cooling has emerged as a promising solution for 3D-ICs, offering better thermal and hydraulic performance than conventional microchannel heat sinks. It is also easy to integrate into existing 3D-IC structures, such as through-silicon vias between stacks. The utilization of two-phase flow in micro-pin fins further enhances temperature uniformity and improves the heat transfer coefficient by leveraging latent heat. Nevertheless, predicting thermal performance in micro-pin fin heat sinks under boiling conditions remains challenging owing to intricate geometric shapes and diverse operating conditions. The present lack of correlation or theoretical models poses a significant obstacle. To address this problem, our study employed a Multimodal machine-learning (ML) approach, combining image data capturing boiling patterns of two-phase flow and information about geometric shape and operating conditions, to predict heat transfer characteristics in micro-pin fin heat sinks. We utilized experimental data comprising 155 types of boiling heat transfer data with the dielectric fluid FC-72 in two micro-fin shapes directly etched on Si. Four ML algorithms (XGBoost, LightGBM, Multilayer perceptron (MLP), and Multimodal ML) were employed to predict thermal performance. The correlation coefficient analysis before learning revealed the influence of each type of measurement data on the heater surface temperature during two-phase flow. Prediction accuracy was measured using mean absolute percent error (MAPE), and the results were compared in terms of maximum and average temperature depending on the characteristics of each ML algorithm. Overall, the Multimodal approach demonstrated superior capability in predicting temperature distributions with spatial details, surpassing conventional decision-tree algorithms and MLP in performance. When trained with boiling images, the Multimodal ML model achieved remarkable precision, evidenced by a MAPE of 1.81% for the maximum temperature and 0.84% for the average temperature, highlighting its exceptional accuracy in mapping the heated surface temperature profile. By contrast, the traditional MLP model, which lacked training on boiling images, showed diminished accuracy, with a MAPE of 2.54% for the maximum temperature and 1.77% for the average temperature, indicating a comparative shortfall against the Multimodal model results.

Study on the 12 in. wafer uniformity of high aspect ratio TSV filling by using rotation cathode

In 2.5/3D(2.5/3-dimensional) packages, TSV (Through-Silicon Via) technology is crucial for achieving high performance and low power consumption. However, there are still challenges when it comes to uniformly filling TSVs on 300 mm whole wafers without defects. This study focuses on addressing this issue by designing a rotating cathode carrier with a 300 mm diameter, simulating the plating environment in different areas of a 300 mm wafer. The effects of plating conditions, such as cathode rotational speed and chip mounting position, on the filling of TSV are investigated. The TSV have a hole diameter of 10 μm and a depth of 100 μm.The findings reveal that when the cathode carrier rotates at a speed of 30 rpm, different areas of the analog wafer exhibit complete filling of TSV. Additionally, a surface plating layer with an average thickness of approximately 3 μm is obtained.

Cu Pumping Analysis during Cu/SiO2 Hybrid Bonding using In-situ SPM Imaging

The assessment of Cu pumping (also known as Cu extrusion) during thermal annealing is vital information for the successful execution of hybrid bonding as well as defect-free processing of the through silicon vias (TSV). Unpredicted Cu pumping can pose major reliability issues. Correspondingly, in this study, high-temperature analysis of Cu pumping was conducted utilizing in-situ scanning probe microscopic (SPM) imaging. Cu/SiO2 surfaces with recessed and protruded Cu topographies were produced by chemical mechanical polishing (CMP) and used for Cu pumping investigations. The amount of Cu pumping upon thermal annealing up to 400°C and cooling down to room temperature was precisely quantified. The SPM results were compared with FEM simulation results, and a numerical equation for Cu pumping was proposed, accordingly. It was shown that by using in-Situ SMP imaging, valuable information on the behavior of hybrid Cu/dielectric surfaces can be generated.

Assembly of Ultra-thin MEMS Device on Driver Chip Using Anisotropic Conductive Film

Assembly solution for large-area, ultra-thin, MEMS-based transducer array dies on driver chips has been investigated using dummy Si dies and substrates. The dummy dies have a thickness of 50 μm, a bonding area on the order of 100 mm2 populated with more than a thousand through-silicon vias connecting corresponding metal pads and redistribution layer (RDL) on both sides. The dummy substrates have conventional thickness as well as necessary RDL and pads for bonding and monitoring electrical resistance and stray capacitance of interconnects. Flip-chip interconnection technology based on anisotropic conductive film (ACF) was selected for bonding and characterization. Handling and ACF bonding of ultra-thin dies to rigid substrates were eased by means of glass carriers attached to the inactive side of the dies. Proper bonding parameters were identified, providing sufficiently low interconnect resistance with satisfactory yield. Stray capacitance of interconnects was found in acceptable range, though lower stray capacitance should be further pursued. The results from this work have demonstrated the feasibility of using ACF for assembling large-area, ultra-thin dies on rigid substrates.

Smart Metrology Control of Through Silicon Via Etching Process for High End Devices

In this paper, we report on an innovative process characterization solution that aims to control the uniformity of the Through Silicon Via (TSV) etching process. The solution relies on measuring complementary geometric characteristics of the open Through-Silicon-VIA (TSV) that are key to establish a reliable vertical interconnection. When TSV are fabricated either in high-density matrix or in isolated locations, the solution presented here allows the non-destructive reliable measurement of top / bottom diameter, depth, and thickness of top hard mask layer with a combination of optical techniques. As example of use case, we present the result of the characterization of three different products hosting TSV with top diameter as small as 3 μm and aspect ratio up to 17:1. The new methodology is compared to the state of the art of metrology control solutions used in the semiconductor industry.

Impact of Cu Protrusion on Connection Resistance in Hybrid Bonding of Via-middle TSV Wafer

In this study, we investigated the impact of Cu protrusion on the connection resistance as detailed data regarding the hybrid bonding of the via-middle through-silicon-via (TSV) wafer. After several Cu TSV wafers and Cu electrode wafers with different amounts of Cu protrusion were prepared and bonded via a surface-activated bonding method using ultrathin Si films, the connection resistance of bonded wafers (that is, the sum of the TSV, Cu electrode, and interface resistances) was evaluated via four-terminal measurements. The results demonstrate that the amount of Cu protrusion is a crucial parameter for the hybrid bonding of via-middle TSV wafers with ultrathin Si films, and an electrical connection between the TSV and Cu electrode can be achieved without heat treatment by adjusting the Cu protrusion.

A Design Method and Application of Meta-Surface-Based Arbitrary Passband Filter for Terahertz Communication.

A meta-surface-based arbitrary bandwidth filter realization method for terahertz (THz) future communications is presented. The approach involves integrating a meta-surface-based bandstop filter into an ultra-wideband (UWB) bandpass filter and adjusting the operating frequency range of the meta-surface bandstop filter to realize the design of arbitrary bandwidth filters. It effectively addresses the complexity of designing traditional arbitrary bandwidth filters and the challenges in achieving impedance matching. To underscore its practicality, the paper employs silicon substrate integrated gap waveguide (SSIGW) and this method to craft a THz filter. To begin, design equations for electromagnetic band gap (EBG) structures were developed in accordance with the requirements of through-silicon via (TSV) and applied to the design of the SSIGW. Subsequently, this article employs equivalent transmission line models and equivalent circuits to conduct theoretical analyses for both the UWB passband and the meta-surface stopband portions. The proposed THz filter boasts a center frequency of 0.151 THz, a relative bandwidth of 6.9%, insertion loss below 0.68 dB, and stopbands exceeding 20 GHz in both upper and lower ranges. The in-band group delay is 0.119 ± 0.048 ns. Compared to reported THz filters, the SSIGW filter boasts advantages such as low loss and minimal delay, making it even more suitable for future wireless communication.

Interface Reliability Modeling of Coaxial Through Silicon Via Based on WOA-BP Neural Network

Abstract Due to the complex structure and thermal mismatch of coaxial through silicon via (TSV), cracks easily occur under thermal load, leading to interface delamination or spalling failure. The reliability issue of coaxial TSV is important for its application in three-dimensional packaging, so it is of great significance to predict the crack trend and evaluate the reliability of coaxial TSV. In this paper, an algorithm model with the combination of whale optimization algorithm (WOA) and back propagation (BP) neural network for the reliability prediction of coaxial TSV is proposed. Based on finite element method (FEM), the training and validation datasets of the energy release rates (ERR) of the crack at the critical interface are calculated to construct the deep learning neural network. Six key structure parameters affecting the reliability of coaxial TSV are selected as the input values of the BP neural network. The maximum relative error of whale optimization algorithm optimized back propagation (WOA-BP) neural network model is 0.88%, which is better than the prediction results of the traditional BP and genetic algorithm (GA) optimized BP models. The WOA-BP neural network model was also compared with BP and GA-BP neural network models with four error metric models. It is verified that WOA-BP neural network model has the best prediction performance. The proposed model can be used to achieve improved prediction accuracy for the interface reliability of coaxial TSV under complex structural conditions since it has higher accuracy and stronger robustness.

Wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan-style Josephson junctions for superconducting quantum processors

We investigate die-level and wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan-style Josephson junctions, using multiple substrates with and without through-silicon vias (TSVs). Dolan junctions fabricated on planar substrates have the highest yield and lowest room-temperature conductance spread, equivalent to ∼100MHz in transmon frequency. In TSV-integrated substrates, Dolan junctions suffer most in both yield and disorder, making Manhattan junctions preferable. Manhattan junctions show pronounced conductance decrease from wafer center to edge, which we qualitatively capture using a geometric model of spatially-dependent resist shadowing during junction electrode evaporation. Analysis of actual junction overlap areas using scanning electron micrographs supports the model, and further points to a remnant spatial dependence possibly due to contact resistance.

Memory built-in self-repair and correction for improving yield: a review

Nanometer memories are highly prone to defects due to dense structure, necessitating memory built-in self-repair as a must-have feature to improve yield. Today’s system-on-chips contain memories occupying an area as high as 90% of the chip area. Shrinking technology uses stricter design rules for memories, making them more prone to manufacturing defects. Further, using 3D-stacked memories makes the system vulnerable to newer defects such as those coming from through-silicon-vias (TSV) and micro bumps. The increased memory size is also resulting in an increase in soft errors during system operation. Multiple memory repair techniques based on redundancy and correction codes have been presented to recover from such defects and prevent system failures. This paper reviews recently published memory repair methodologies, including various built-in self-repair (BISR) architectures, repair analysis algorithms, in-system repair, and soft repair handling using error correcting codes (ECC). It provides a classification of these techniques based on method and usage. Finally, it reviews evaluation methods used to determine the effectiveness of the repair algorithms. The paper aims to present a survey of these methodologies and prepare a platform for developing repair methods for upcoming-generation memories.

Gamma-Ray Irradiation Induced Dielectric Loss of SiO2/Si Heterostructures in Through-Silicon Vias (TSVs) by Forming Border Traps

Gamma-Ray Irradiation Induced Dielectric Loss of SiO₂/Si Heterostructures in Through-Silicon Vias (TSVs) by Forming Border Traps

Genetic Algorithm Based 3D IC Partitioning Approach for TSV Minimization and Efficient Layer Assignment

The rise of three-dimensional (3D) IC layouts necessitates the development of unique partitioning methods that will be suitable for the 3D component designs. Net lists partitioning is a key aspect of the physical design of a 3D IC. Reducing wire lengths between gates is possible with 3D-ICs since they have a small footprint as well as vertical connectivity among dies. As a result, they consume less power and have shorter connection delays. This paper presents an efficient genetic algorithm (GA) based layer partitioning technique for 3D ICs that focuses on proper layer assignment to reduce area deviation and minimization of Through Silicon Vias (TSVs) to reduce IC footprint. The method starts with random initial solutions and refines the solutions with efficient crossover and mutation operator till the optimized solution is achieved. Our methodology produces high-quality solutions on well-known benchmarks. The experimental findings are compared with state-of-the-art methodologies and the suggested strategy is found to be very effective in the case of decreasing the TSV count and space need of the 3-dimensional IC design. In addition, the performance of our strategy is also compared with two recent publications that use GA and Particle Swarm Optimization (PSO) and it is found that the proposed method achieves 20.18% and 38.66% average reduction in terms of TSV count respectively. Thus, the suggested technique is beneficial for multilayered 3D IC partitioning, as it can reduce TSV count while also satisfying balancing criteria and latency.