Through Silicon Via Research Articles

Simulation study and parameter optimization of laser TSV using artificial neural networks

Through-Silicon Vias (TSV) play an important role in the field of semiconductor 3D packaging by providing interconnections during layer-by-layer stacking. Laser machining of TSVs is advantageous over expensive photolithography steps in the DRIE process. It is environmentally friendly, reduces production costs, and increases throughput. In this study, a nanosecond laser (100 ns, 1064 nm) was used to produce TSVs on a 500 μm thick silicon wafer, and the effects on parameters such as drilling depth, aspect ratio, taper angle, and heat-affected zone (HAZ) were investigated in air. Furthermore, an optimized circle-packing design between pulse energy (E) and the number of pulses (N) was constructed. The developed computational model was employed to run simulations to predict the drilling depth, aspect ratio, taper angle, and HAZ. Subsequently, the obtained results were used to train surrogate models for all individual parameters in the given range. A final processing map was created by combining all the individual surrogate models and filtered with four criteria to obtain the optimized region with proper drilling depth, less taper angle, high aspect ratio, and comparatively less HAZ TSVs. Lastly, points were chosen from each region, and experiments were performed to validate the optimized zone, and full agreement was found with the simulation results. With this optimized zone, TSVs with a higher aspect ratio (11.72), less taper angle (1.37°), and comparatively less HAZ thickness (10.48 μm) were achieved for the combination of pulse energy at 0.3614 mJ and pulse number at 835.

Recent Advances and Trends in Chiplet Design and Heterogeneous Integration Packaging

Abstract In this study, chiplet design and heterogeneous integration packaging, especially (a) chip partition and heterogeneous integration driven by cost and technology optimization, Figs. 1(a) and 1(b) chip split and heterogeneous integration driven by cost and yield, Figs. 1(b) and 1(c) multiple system and heterogeneous integration with thin-film layers directly on top of a build-up package substrate, Figs. 1(c) and 1(d) multiple system and heterogeneous integration with an organic interposer on top of a build-up package substrate, Figs. 1(d) and 1(e) multiple system and heterogeneous integration with through-silicon via (TSV) interposer on top of a build-up package substrate, Fig. 1(e), will be investigated. Figures 1(c)–1(e) are driven by formfactor and performance. Emphasis is placed on their advantages and disadvantages, design, materials, process, and examples. Some recommendations will also be provided.

Parameter analysis and electrochemical properties of 4,6-Dimethyl-2-mercaptopyrimidine for mitigating Cu prominence in through silicon vias filling

Through silicon via (TSV) is the core technology that implements three-dimensional (3D) integrated packaging in integrated circuits. Electrodeposition defects affect the reliability of TSVs. In particular, the surface Cu protrusions can lead to structural deformations, which significantly affect the reliability of TSVs. In this study, 4,6-Dimethyl-2-mercaptopyrimidine (DMP) is studied as a leveller additive for TSV electroplating, along with the effect of the deposition parameters on the TSV filling process and surface morphology. To evaluate the filling performance of DMP, linear sweep voltammetry (LSV) is performed to investigate how the additives affect the filling mechanism. Finally, the conditions of this levelling agent in TSV plating are predicted based on LSV curves and validated using plating experiments.

Design of a Novel Compact Bandpass Filter Based on Low-Cost Through-Silicon-Via Technology.

Three-dimensional (3D) integration based on through-silicon-via (TSV) technology provides a solution to the miniaturization of electronic systems. In this paper, novel integrated passive devices (IPDs) including capacitor, inductor, and bandpass filter are designed by employing TSV structures. For lower manufacturing costs, polyimide (PI) liners are used in the TSVs. The influences of structural parameters of TSVs on the electrical performance of the TSV-based capacitor and inductor are individually evaluated. Moreover, with the topologies of capacitor and inductor elements, a compact third-order Butterworth bandpass filter with a central frequency of 2.4 GHz is developed, and the footprint is only 0.814 mm × 0.444 mm. The simulated 3-dB bandwidth of the filter is 410 MHz, and the fraction bandwidth (FBW) is 17%. Besides, the in-band insertion loss is less than 2.63 dB, and the return loss in the passband is better than 11.4 dB, showing good RF performance. Furthermore, as the filter is fully formed by identical TSVs, it not only features a simple architecture and low cost, but also provides a promising idea for facilitating the system integration and layout camouflaging of radio frequency (RF) devices.

An end-to-end convolutional neural network for automated failure localisation and characterisation of 3D interconnects

The advancement in the field of 3D integration circuit technology leads to new challenges for quality assessment of interconnects such as through silicon vias (TSVs) in terms of automated and time-efficient analysis. In this paper, we develop a fully automated high-efficient End-to-End Convolutional Neural Network (CNN) model, utilizing two sequentially linked CNN architectures, suitable to classify and locate thousands of TSVs as well as provide statistical information. In particular, we generate interference patterns of the TSVs by conducting a unique concept of Scanning Acoustic Microscopy (SAM) imaging. Scanning Electron Microscopy (SEM) is used to validate and also disclose the characteristic pattern in the SAM C-scan images. By comparing the model with semi-automated machine learning approaches its outstanding performance is illustrated, indicating a localisation and classification accuracy of 100% and greater than 96%, respectively. The approach is not limited to SAM-image data and presents an important step towards zero defect strategies.

The Analysis of Multiwall Carbon Nanotubes as Through Silicon Via by Equivalent Circuit Model at Different Operating Temperatures in Multilayers Stacking Scheme

In nowadays 3-D integrated circuits (3DICs) technology, through silicon via (TSV) is the most important component, which connects homogeneous or heterogeneous dies vertically with each other. Based on our previous research, carbon nanotubes (CNTs) have been considered as TSV filling materials due to their outstanding mechanical and electrical properties. However, the operating temperatures would significantly affect the performance of signal transmission in CNT TSV. To evaluate the electrical characteristics of CNT TSV with different realistic temperatures, the considerations of temperature-dependent electron mean free path (MFP, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\uplambda \text{)}$</tex-math> </inline-formula> , and number of conducting channels of CNTs are necessary. In this work, the equivalent circuit model of CNTs as TSV is presented and the simulated electrical behaviors are benchmarked with other literatures. Based on our proposed model, multiwall (MW) CNTs’ electrical performance in multilayers stacking system under different operating temperatures is investigated. In addition, we also compare the electrical performance of CNTs as TSV with the conventional filling material (Cu). It shows that CNT TSV has more advantages than Cu TSV when the operating temperature becomes higher. In summary, the proposed equivalent circuit model in this work is more comprehensive and yields more realistic results. Meanwhile, CNT is a promising material for TSV under varying operation temperatures.

A Miniaturized Wideband SIR Interdigital Bandpass Filter With High Performance Based on TSV Technology for W-Band Application

In this paper, an ultra-compact wideband stepped impedance resonators (SIR) interdigital bandpass filter (IBPF) is proposed based on through-silicon via (TSV) and three-dimensional integrated circuit (3D IC) technology. SIR structure can achieve higher coupling strength at a small impedance ratio. On this basis, the IBPF is designed by exploiting λ/4 SIR, the proposed filter is realized with compact size and far parasitic passband, and exhibits superior fractional bandwidth and out of band suppression characteristics. Based on the transformation of Chebyshev low-pass circuit model, a seventh-order IBPF centered at 98.5GHz is obtained. An improved method combining TSV technology with coupling coefficient method is proposed, which simplifies the design process and improves the influence of parasitic inductance on the design process. The fractional bandwidth (FBW) of SIR IBPF based on TSV is 40%, the insertion loss is less than 1.3dB, and a reflection of better than 30 dB in the passband. The size of the compact SIR IBPF is only 0.24×0.7mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (0.28 × 0.79 λg <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ).

Modeling and Validation of Total Ionizing Dose Effect on the TSVs in RF Microsystem.

Radio frequency (RF) systems utilizing through-silicon vias (TSVs) have been widely used in the aerospace and nuclear industry, which means that studying the total ionizing dose (TID) effect on TSV structures has become necessary. To investigate the TID effect on TSV structures, a 1D TSV capacitance model was established in COMSOL Multiphysics (COMSOL), and the impact of irradiation was simulated. Then, three types of TSV components were designed, and an irradiation experiment based on them was conducted, to validate the simulation results. After irradiation, the S21 degraded for 0.2 dB, 0.6 dB, and 0.8 dB, at the irradiation dose of 30 krad (Si), 90 krad (Si), 150 krad (Si), respectively. The variation trend was consistent with the simulation in the high-frequency structure simulator (HFSS), and the effect of irradiation on the TSV component was nonlinear. With the increase in the irradiation dose, the S21 of TSV components deteriorated, while the variation of S21 decreased. The simulation and irradiation experiment validated a relatively accurate method for assessing the RF systems' performance under an irradiation environment, and the TID effect on structures similar to TSVs in RF systems, such as through-silicon capacitors.

Fast power density aware three‐dimensional integrated circuit floorplanning for hard macroblocks using best operator combination genetic algorithm

AbstractIn this article, we propose a fast three‐dimensional integrated circuit (3D‐IC) floorplanning method for hard macroblocks that includes a thermal management scheme. It applies a genetic algorithm constituted by an optimal combination of crossover and mutation operations to identify the optimal solution for design variables, namely, total wire length, number of through‐silicon vias (TSVs), and maximum average layer power density. The proposed method additionally makes use of a unique TSV placement scheme that arranges TSVs next to their respective functional blocks. To enable efficient heat transmission to the ambient environment, layers with higher power densities are placed closer to the heat sink. The proposed 3D‐IC floorplanning approach provides the fewest TSVs, the lowest peak temperature, and promising values of wire length within the least amount of computation time. Compared to the recent fast thermal analysis for fixed‐outline 3D‐floorplanning, it generates 13.14% shorter wire length, 39.27% lower peak temperature, and 34.35% lesser number of TSVs on average with significant improvement in computation time, while analyzing GSRC thermal benchmark circuits.

Fabrication and Characterization of Thin Metal Films Deposited by Electroless Plating with Organic Additives for Electrical Circuits Applications.

In our work, we studied thin nickel films deposited by electroless plating for use as a barrier and seed layer in the through-silicon vias (TSV) technology. El-Ni coatings were deposited on a copper substrate from the original electrolyte and with the use of various concentrations of organic additives in the composition of the electrolyte. The surface morphology, crystal state, and phase composition of the deposited coatings were studied by SEM, AFM, and XRD methods. The El-Ni coating deposited without the use of an organic additive has an irregular topography with rare phenocrysts of globular formations of hemispherical shape and a root mean square roughness value of 13.62 nm. The phosphorus concentration in the coating is 9.78 wt.%. According to the results of the X-ray diffraction studies of El-Ni, the coating deposited without the use of an organic additive has a nanocrystalline structure with an average nickel crystallite size of 2.76 nm. The influence of the organic additive is seen in the smoothening of the samples surface. The root mean square roughness values of the El-Ni sample coatings vary within 2.09-2.70 nm. According to microanalysis data the phosphorus concentration in the developed coatings is ~4.7-6.2 wt.%. The study of the crystalline state of the deposited coatings by X-ray diffraction made it possible to detect two arrays of nanocrystallites in their structure, with average sizes of 4.8-10.3 nm and 1.3-2.6 nm.

A novel chip-scale heterogeneous integration intelligent micro-system of short wave infrared imaging

In this paper, a novel heterogeneous integrated intelligent micro sensing system for short-wave infrared (SWIR) sensing and processing is proposed, which can detect and recognize objects based on image signals, and realize the complete function of “sensing-process-communication” at the chip scale. Here, we innovatively adopt chip scale heterogeneous integration (CSHI) to achieve high-density integration of sensor, analog and digital chips with different substrates and different process nodes by vertically interconnecting the 2.5 dimension (2.5 D) Through-Silicon Via (TSV) silicon interposer and 3 dimension (3D) high temperature co-fired ceramics (HTCC) ceramics. The short-wave infrared image detection and recognition system with high performance, small size and high reliability is realized on the premise of maintaining good interconnect power supply and signal integrity, and the feasibility of the proposed comprehensive approach is verified. Sensors, analog and digital chips of different substrates and process nodes are integrated into a micro-system at the chip level through this approach. The approach presented in this paper is an effective solution to realize intelligent sensing micro-system, which can effectively extend functions and improve integration level at the chip scale.

TSV-based SIW bandpass filter with adjustable transmission zeros for D-band applications

A substrate integrated waveguide (SIW) bandpass filter with adjustable out of band transmission zeros based on through-silicon via (TSV) technology is proposed. The single-cavity degenerate mode is separated by the metal via-hole and the defect grounding structure, which is coupled with other cavities to generate transmission zeros with adjustable positions and increase the out of band roll-off rate. The results show that, the center frequency of the filter is 148GHz, the bandwidth is 6.5GHz, the minimum insertion loss is 1.4dB, and the return loss is better than 20.4dB.

Miniaturized silicon-based substrate integrated waveguide filter for 6G applications

Based on Through-Silicon Via (TSV) technology, a Substrate Integrated Waveguide (SIW) bandpass filter with ultra-compact size is presented for sixth-generation (6G) mobile communication applications. The proposed filter is proposed by the way of the generalized Chebyshev filters and coupling matrix reconfiguration. The measurement results reveal that the out-of-band rejection is better than 25 dB with frequencies up to 1.059 f0. In addition, the proposed filter has the center frequency of the passband at 0.371 THz with bandwidth of 0.0183 THz. The size is only 0.496 × 0.33 mm2.

Wearable Multi-Channel Pulse Signal Acquisition System Based on Flexible MEMS Sensor Arrays with TSV Structure.

Micro-electro-mechanical system (MEMS) pressure sensors play a significant role in pulse wave acquisition. However, existing MEMS pulse pressure sensors bound with a flexible substrate by gold wire are vulnerable to crush fractures, leading to sensor failure. Additionally, establishing an effective mapping between the array sensor signal and pulse width remains a challenge. To solve the above problems, we propose a 24-channel pulse signal acquisition system based on a novel MEMS pressure sensor with a through-silicon-via (TSV) structure, which connects directly to a flexible substrate without gold wire bonding. Firstly, based on the MEMS sensor, we designed a 24-channel pressure sensor flexible array to collect the pulse waves and static pressure. Secondly, we developed a customized pulse preprocessing chip to process the signals. Finally, we built an algorithm to reconstruct the three-dimensional pulse wave from the array signal and calculate the pulse width. The experiments verify the high sensitivity and effectiveness of the sensor array. In particular, the measurement results of pulse width are highly positively correlated with those obtained via infrared images. The small-size sensor and custom-designed acquisition chip meet the needs of wearability and portability, meaning that it has significant research value and commercial prospects.

Electromigration in three-dimensional integrated circuits

The development of big data and artificial intelligence technology is increasing the need for electronic devices to become smaller, cheaper, and more energy efficient, while also having enhanced functionalities. However, the miniaturization of silicon chip technology is approaching its Moore's law (i.e., physical) limits. Thus, the application of three-dimensional integrated circuits (3D ICs), in which multiple chips are stacked vertically, provides the most achievable approach for the advancement of post-Moore electronics. In the recent decade, various key techniques have been developed for stacking chips vertically such as through-silicon vias, micro-bumps, low melting point tin–bismuth solders, redistribution layers, and copper-to-copper direct bonding. However, the need for high current densities in these structures results in severe Joule heating, making electromigration (EM) an increasingly challenging problem. This paper reviews studies on EM failures, mechanisms, and potential solutions for the key components of 3D IC packaging.

Modelling and analysis of contactless sensor for TSV fault based on resonant inductive coupling

In order to solve the problems of inefficient detection, high cost, and high damage rate of existing Through Silicon Via (TSV) contact detection, contactless testing techniques are urgently needed to eliminate the many problems associated with contact. In this paper, a contactless antenna utilizing resonant inductive coupling is presented. This coupling method, as compared to the conventional capacitive coupling technique allows faults detect from longer distances. The results of 3D full wave simulations in the High Frequency Structure Simulator (HFSS) and Advanced Design System (ADS) show that various faults, such as voids and pinholes, can be detected when the distance between the TSV and the antenna remains about 10 μm. Defective TSVs cause changes in the operating current and voltage pulses at the detection antenna. Simultaneously, changes in the field distribution around the TSVs are used to explain the changes in current and voltage pulses. Furthermore, the effects of antenna parallel movement were also investigated.

Mosaic-3C1S: A Low Overhead Crosstalk Suppression Scheme for Rectangular TSV Array

The through silicon via (TSV) is one of the important enabling technologies of stacked 3D ICs. However, the crosstalk is generated when signals are transmitted through the closely clustered TSVs due to the coupling effect. The crosstalk avoidance code (CAC) techniques have attracted great concerns in recent years, for the TSV-to-TSV crosstalk deteriorates the signal integrity. Nevertheless, the CAC techniques usually require specific shape of TSV array, e.g. 3×N array. This work proposes a crosstalk suppression scheme combining the CAC method and the static shielding technique, named as Mosaic-3C1S. The proposed scheme is able to be applied to arbitrary rectangular TSV arrays. In the proposed scheme, the 2×2 TSV sub-array which contains three signal TSVs and one shielding TSV, is used as the basic unit to tile the rectangular TSV array. The CAC method is applied to the signal TSVs in the 2×2 sub-arrays, and the raw data are transmitted by the rest boundary TSVs, if any. In order to further reduce the bit overhead, a triangular numeral system based CAC, named as TNS-CAC, is proposed and applied. The simulation results show that the proposed TNS-CAC has advantages on bit overhead and codec area. And the proposed Mosaic-3C1S scheme with TNS-CAC is able to suppress the crosstalk between TSVs to 6C level. The bit overhead of the proposed scheme is between 25% 45%, which is lower than that of the previous CAC methods for TSV arrays for the most cases.

Signal Integrity Analysis of Through-Silicon Via (TSV) With a Silicon Dioxide Well to Reduce Leakage Current for High-Bandwidth Memory Interface

In this paper, we propose and analyze a through silicon via (TSV) with a silicon dioxide well (SDW) to reduce leakage current in the design of a high-speed signaling and low-power consumption high-bandwidth memory (HBM) interface. In the proposed TSV, the SDW is inserted into the silicon substrate area between TSVs. By inserting the SDW, the silicon substrate’s effective conductivity and permittivity are lowered compared to a conventional TSV. The proposed TSV with the SDW improves insertion loss by up to 0.079 dB at 4 GHz by minimizing the leakage current. In addition, by reducing the effective permittivity of the silicon substrate, the difference in ratio between the capacitive coupling and inductive coupling is minimized. It is also possible to obtain a reduction in far-end crosstalk (FEXT) in the range of HBM interface signaling. RLGC modeling of the proposed TSV with the SDW is presented, and is physically analyzed based on the frequency-dependent equivalent capacitance and conductance of the silicon substrate. The proposed TSV with SDW is finally evaluated using an eye diagram, and the eye height and width improved by up to 13.7 % and 4.7 % at 8 Gb/s, respectively, compared to the conventional TSV. The proposed TSV also reduced dynamic power consumption by 48.1 % at 8 Gb/s, verifying the low-power structure.

A Dry Etch Approach To Reduce Roughness and Eliminate Visible Grind Marks in Silicon Wafers Post Back-Grind

3D wafer packaging represents a significant component of the total wafer level processing cost. Replacement of the Chemical Mechanical Polishing (CMP) process step with a corresponding dry etch can yield significant time and cost savings. Incorporating equipment already utilized in the 3D integrated wafer packaging process during the subsequent Through Silicon Via (TSV) reveal step, process efficiencies can be achieved, with overall die yields being maintained. Using dry etch technology to treat a 200nm rough back-ground silicon surface, a smooth surface with a peak to valley roughness of less than 6nm is demonstrated. This patented process differs from other dry etch smoothing techniques in that it aims to eliminate any visual grind marks rather than just reducing the surface roughness. The elimination of visible grind marks is critical in later optical inspection where they are falsely identified as defects. The quality of the surface is equivalent to that of a CMP processed wafer and as such, this process has been implemented in manufacturing replacing the CMP step. The novel process described combines a surface modification followed by a roughness reduction in an iterative manner to produce a smooth surface without visible grind marks post processing.

Rapid realization of ultra-high vacuum packaging of atomic chips by thick film technology

This research is an attempt to apply the silver thick-film metallization and the soft soldering process to the ultra-high vacuum packaging of atom chips with through silicon via (TSV). During the packaging process, a vacuum environment is used to avoid oxidation of the Cu layer on the chip during heating. At the same time, tin foil is used to protect the inner wall of the glass cell to prevent the gas emitted by the solder from polluting the inner wall. In general, by the adoption of screen printing, sintered surface metallization at a constant temperature of 450–500 °C for 5 min, combined with soft soldering, the packaging of an atom chip with TSV and a silica glass cell is realized. The weld gap is less than 50 μm, the airtightness can reach 8.5 × 10−13 Pa m3/s, and the vacuum degree can reach 2.18 × 10−8 Pa. That can meet the requirements of cold atom experiment for light path and vacuum degree.