Through Silicon Via Technology Research Articles

Study on the 12 in. wafer uniformity of high aspect ratio TSV filling by using rotation cathode

In 2.5/3D(2.5/3-dimensional) packages, TSV (Through-Silicon Via) technology is crucial for achieving high performance and low power consumption. However, there are still challenges when it comes to uniformly filling TSVs on 300 mm whole wafers without defects. This study focuses on addressing this issue by designing a rotating cathode carrier with a 300 mm diameter, simulating the plating environment in different areas of a 300 mm wafer. The effects of plating conditions, such as cathode rotational speed and chip mounting position, on the filling of TSV are investigated. The TSV have a hole diameter of 10 μm and a depth of 100 μm.The findings reveal that when the cathode carrier rotates at a speed of 30 rpm, different areas of the analog wafer exhibit complete filling of TSV. Additionally, a surface plating layer with an average thickness of approximately 3 μm is obtained.

A compact fifth-order SIW BPF based on TSV technology with high selectivity

In this paper, a fifth-order Substrate Integrated Waveguide (SIW) filter using Through-Silicon Via (TSV) technology is proposed. The slots on the top and bottom redistribution layers (RDL) of the filter provide negative coupling and a finite transmission zero (FTZ). This effectively improves stopband attenuation. Asynchronous tuning is applied to the coupling path of this component. The center frequency of the filter is 3.6 GHz (fractional bandwidth is 3.50 %). The minimum insertion loss is 1.58 dB, the minimum return loss is 23.6 dB, and the overall size is 1.855 × 1.316 mm2. The simulation results show that the proposed SIW filter can achieve better in-band characteristics and selectivity with the similar size or smaller size as compared to the SIW filter operating at the similar frequency.

High-temperature adaptive through-silicon via with pyrolyzed carbon via-sealing plates for packaging 3D carbon nanostructure-based devices fabricated using C-MEMS

Through-silicon via (TSV) is a key packaging technology that facilitates the 2.5D/3D integration of microelectromechanical system (MEMS) devices. Among various MEMS technologies, C-MEMS enables micro/nanoscale 3D carbon structure manufacturing using high-temperature (600–1200 °C) pyrolysis. These high-temperature conditions limit the application of conventional TSV technologies to C-MEMS devices. This study presents a novel TSV with carbon via-sealing plates that are adaptable to C-MEMS device packaging. Via holes are drilled before integrating the MEMS device to protect the delicate micro/nanoscale structures. Moreover, the topside via inlet is sealed with a thin conductive pyrolyzed carbon plate to prevent the contamination of the via interior during the C-MEMS process and ensure an electrical connection between the devices and the vias. After integrating the C-MEMS devices, TSV fabrication is completed by coating the via inside with a metal layer from the wafer's bottom side, achieving a conductance per unit area of approximately 327 S/mm2 (via diameter = 33 μm, length = 100 μm). The applicability of the proposed wafer-level TSV technology to C-MEMS devices is then verified through the implementation of a suspended carbon nanowire-based gas sensor integrated with the developed TSV, which exhibits excellent signal transmission. Furthermore, the proposed TSV packaging technology can be applied to various micro/nanofabrication technologies because of its high-temperature/wet-process compatibility and cost-effective fabrication.

AdEle+: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D Networks-on-Chip

Unlike conventional 2D Networks-on-Chip (NoCs), 3D NoCs offer a scalable and energy efficient on-chip communication. Vertical die stacking of 3D NoCs is enabled using inter-layer Through-Silicon Via (TSV) links. However, TSV technology suffers from low reliability and high fabrication costs. To mitigate these costs, Partially Connected 3D NoCs (PC-3DNoCs), which use fewer vertical TSV links, have been introduced. However, with fewer vertical links (a.k.a. elevators), elevator-less routers will have to send their traffic to nearby elevators for inter-layer traffic, increasing the traffic load and congestion at these elevators and potentially reducing performance. Therefore, it is important that elevator-less routers choose elevators that balance the traffic load among the available elevators. To address this problem, this paper presents an <underline xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ad</u> aptive congestion- and energy-aware <underline xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ele</u> vator-selection algorithm, called AdEle+. AdEle+ employs an offline multi-objective simulated-annealing-based optimization to find good elevator subsets for routers. In addition, during high traffic loads, AdEle+ uses an adaptive and online elevator selection algorithm to select an elevator from the elevator subset to dynamically manage traffic congestion on elevators. Moreover, in low congestion circumstances, AdEle+ switches to a minimal distance selection to improve energy efficiency. Compared to state-of-the-art selection algorithms under various PC-3DNoC configurations and traffic patterns, AdEle+ reduces the average latency by 9.5% on average and up to 11.2% while reducing the hardware overhead by 10.1% due to its efficient online selection in the routers.

Research of Vertical via Based on Silicon, Ceramic and Glass.

With the increasing demand for high-density integration, low power consumption and high bandwidth, creating more sophisticated interconnection technologies is becoming increasingly crucial. Three-dimensional (3D) integration technology is known as the fourth-generation packaging technology beyond Moore's Law because of its advantages of low energy consumption, lightweight and high performance. Through-silicon via (TSV) is considered to be at the core of 3D integration because of its excellent electrical performance, lower power consumption, wider bandwidth, higher density, smaller overall size and lighter weight. Therefore, the particular emphasis of this review is the process flow of TSV technology. Among them, the research status of TSV hole etching, deep hole electroplating filling and chemical mechanical planarization (CMP) in TSV preparation process are introduced in detail. There are a multitude of inevitable defects in the process of TSV processing; thus, the stress problems and electrical characteristics that affect the reliability of TSV are summarized in this review. In addition, the process flow and process optimization status of through ceramic via (TCV) and through glass via (TGV) are discussed.

Etching mechanism of high-aspect-ratio array structure

Through-Silicon-Via (TSV) is an significant technology that is being widely employed in micro-electro-mechanical system (MEMS) manufactories. However, it is remain challenging to obtain a deep silicon etching with vertical-angle and smooth-sidewall characterizes by silicon-etching anisotropy through TSV technology. Herein, we use inductively coupled plasma (ICP) to obtain the deep silicon etching anisotropy. Chamber pressure, Bosch process cycles, bias powers, and the size of the etching pattern, which are the critical controllable process parameters, have been investigated to achieve the silicon-etching anisotropy. The results reveal that the sidewall angle of the array structure becomes increasingly slanted while raising chamber pressure from 2 to 15 Pa in the SF6 etching process of the first step of the cycle in the Bosch process. As the cycles increase from 60 to 240 cycles at the bias power of 100 w, the anisotropy decreases from 0.80 to 0.5. With RF bias powers rise from 200 to 400 w, the anisotropy enhances from 0.80 to 0.94. Due to the collision of active ions with each other, the sidewall angle and anisotropy of a high aspect-ratio array structure severely depend on the incidence angle of the active ions. The “Si etching balance model” has been established for the fabrication of TSV.

A Miniaturized Wideband SIR Interdigital Bandpass Filter With High Performance Based on TSV Technology for W-Band Application

In this paper, an ultra-compact wideband stepped impedance resonators (SIR) interdigital bandpass filter (IBPF) is proposed based on through-silicon via (TSV) and three-dimensional integrated circuit (3D IC) technology. SIR structure can achieve higher coupling strength at a small impedance ratio. On this basis, the IBPF is designed by exploiting λ/4 SIR, the proposed filter is realized with compact size and far parasitic passband, and exhibits superior fractional bandwidth and out of band suppression characteristics. Based on the transformation of Chebyshev low-pass circuit model, a seventh-order IBPF centered at 98.5GHz is obtained. An improved method combining TSV technology with coupling coefficient method is proposed, which simplifies the design process and improves the influence of parasitic inductance on the design process. The fractional bandwidth (FBW) of SIR IBPF based on TSV is 40%, the insertion loss is less than 1.3dB, and a reflection of better than 30 dB in the passband. The size of the compact SIR IBPF is only 0.24×0.7mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (0.28 × 0.79 λg <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ).

A hexagonal high-performance transformer balun based on TSV technology for W-band application

Balun has been widely used for microwave circuits for its balance properties. The development of highly integrated RF systems has put forward higher requirements for superior performance and miniaturization of the balun. A compact broadband millimeter wave (MMW) transformer balun based on through silicon via (TSV) technology is proposed in this letter. Compared with the traditional balun, the proposed balun impedance ratio is 4:1, and the use of hexagonal coil winding significantly reduces its area and improves its performance. It is shown that the proposed balun has a magnitude imbalance of 0.64dB and a phase imbalance of 2.5° at 81.5-93GHz. A return loss of greater than 15dB is obtained for the frequency band ranges from 82.1-88.6 GHz. Furthermore, the area of balun is only 0.201×0.29mm2 (0.2×0.29λg2).

A 3-D Integrated Common Mode Filter Based on Through Silicon vias Technology

Common mode filters (CMF) are widely used to ensure signal integrity. However, due to the large area, traditional CMFs cannot meet the eager demand for the miniaturization of modern communication systems. In this paper, a three-dimensional integrated CMF based on through silicon vias (TSV) technology is proposed. The adoption of TSV technology greatly reduces the area of CMF. The structure is modeled and simulated by HFSS software. The stopband of the common mode signal is 7.9 GHz ~ 18.8 GHz. In the operating frequency band, the effect of group delay jitter on frequency is less than 10 ps. Moreover, the plane area of the CMF is only 0.195 mm2.

Testing station for fast screening of through silicon via-enabled application-specific integrated circuits for hard x-ray imaging detectors

Application-specific integrated circuits (ASICs) are used in space-borne instruments for signal processing and detector readout. The electrical interface of these ASICs to frontend printed circuit boards is commonly accomplished with wire bonds. Through silicon via (TSV) technology has been proposed as an alternative interconnect technique that will reduce assembly complexity of ASIC packaging by replacing wire bonding with flip-chip bonding. TSV technology is advantageous in large detector arrays where TSVs enable close detector tiling on all sides. Wafer-level probe card testing of TSV ASICs is frustrated by solder balls introduced onto the ASIC surface for flip-chip bonding that hamper alignment. Therefore, we developed the ASIC test stand (ATS) to enable rapid screening and characterization of individual ASIC die. We successfully demonstrated ATS operation on ASICs originally developed for CdZnTe detectors on the Nuclear Spectroscopic and Telescope Array (NuSTAR) mission that were later modified with TSVs in a via-last process. We tested both backside blind-TSVs and frontside through-TSVs, with results from internal test pulser measurements that demonstrate performance equal to or exceeding the probe card wafer-level testing data. The ATS can easily be expanded or duplicated to parallelize ASIC screening for large area imaging detectors of future space programs.

Proof of concept for through silicon vias in application-specific integrated circuits for hard x-ray imaging detectors

Application-specific integrated circuits (ASICs) are commonly used to efficiently process the signals from sensors and detectors in space. Wire bonding is a space-qualified technique of making interconnections between ASICs and their substrate packaging board for power, control, and readout of the ASICs. Wire bonding is nearly ubiquitous in modern space programs, but their exposed wires can be prone to damage during assembly and subject to electric interference during operations. Additional space around the ASICs needed for wire bonding also impedes efficient packaging of large arrays of detectors. Here, we introduce the through silicon vias (TSV) technology that replaces wire bonds and eliminates their shortcomings. We have successfully demonstrated the feasibility of implementing TSVs to existing ASIC wafers (a.k.a. a via-last process) developed for processing the x-ray signals from the x-ray imaging CdZnTe detectors on the Nuclear Spectroscopic Telescope Array small explorer telescope mission that was launched in 2012. While TSVs are common in the semiconductor industry, this is the first (to our knowledge) successful application for astrophysics imaging instrumentation. We expect that the TSV technology will simplify the detector assembly and thus will enable significant cost and schedule savings in assembly of large area CdZnTe detectors.

Area-Efficient Extended 3-D Inductor Based on TSV Technology for RF Applications

An extended model of through-silicon via (TSV)-based solenoid inductor is proposed to save on-chip areas for 3-D radio frequency (RF) ICs and package integration. To achieve a high inductance density, the nested topology consists of high-density TSVs in high-resistivity silicon substrate and multilayers of metals in compatible CMOS process. Then, an analytical inductance model, considering the mutual inductance of TSVs and complicated metal traces, is established and verified. The inductance variation in physical dimensions is studied based on the modeled and simulated results of a TSV solenoid inductor in single tier. The proposed TSV solenoid typology gets better performance at inductance density and quality factor around some frequencies through analytical model and full-wave simulations. Further studies are directed toward RF application overview according to broadband and low power consumption.

Electrical and Mechanical Analysis of Different TSV Geometries

Through-silicon via (TSV) is an important component for implementing 3-D packages and 3-D integrated circuits as the TSV technology allows stacked silicon chips to interconnect through direct contact to help facilitate high-speed signal processing. By facilitating the stacking of silicon chips, the TSV technology also helps to meet the increasing demand for high density and high performance miniaturized electronic products. Our review of the literature shows that very few studies have reported on the impact of TSV bump geometry on the electrical and mechanical characteristics of the TSV. This paper reports on the investigation of different TSV geometries with the focus on identifying the ideal shapes for improved electrical signal transmission as well as for improved mechanical reliability. The cylindrical, quadrangular (square), elliptical, and triangular shapes were investigated in our study and our results showed that the quadrangular shape had the best electrical performance due to good characteristic impedance. Our results also showed that the quadrangular and cylindrical shapes provided improved mechanical reliability as these two shapes lead to high Cu protrusion of TSV after the annealing process.

Nondestructive Methods for Characterizing Copper Electrofilled through Silicon Vias

Developments in through silicon via (TSV) fabrication and filling have allowed for significant advancements in the microelectronics industry by enabling compact 3D integration. Copper, due to its desirable electrical properties, is the most commonly used metal for TSVs filling. TSVs are filled electrochemically by selectively reducing solvated metal ions in an electrolyte solution to confined TSV geometries via the addition of organic and inorganic additives (halides, suppressors, accelerators, levelers). Optimization of this mechanism can often be temperamental requiring alterations in the solution’s chemical makeup as well as electrical bias and fluid flow parameters. Therefore, consistent and reliable methods of characterizing electrochemical copper fill quality is critical to provide feedback necessary for process adjustments. Historically, characterizing TSV fill profile has relied on physical cross sectioning by mechanical grinding, planarization and polishing (Figure 1). These methods are effective in that they offer direct visualization of the TSV fill quality; however, they have certain inherent drawbacks. The most critical drawback is that mechanical cross sectioning is a destructive process and can only be used in process development and not on deliverable parts. Also, mechanical material removal can often be time consuming and inconsistent requiring significant effort by process technicians to generate desirable results. Implementing non-destructive methods for characterization is necessary for the advancement of TSV technology and has been explored in an effort to make TSV research more streamline and efficient. Recent work at Sandia National Laboratories has evaluated non-destructive TSV characterization processes through X-Ray Computed Tomography (CT), digital radiographs and X-ray Phase Contrast Imaging (XPCI). The benefit of X-ray evaluation of TSV filling is batch level processing of many TSVs at once (Figure 2A), digital model rendering for multidimensional analysis (Figure 2B), and complete preservation of the physical integrity of test pieces and deliverables. Each nondestructive technique for TSV characterization will be directly compared and contrasted to conventional grinding and polishing on the merits of defect detection, resolution, time consumption and reproducibility. This talk will outline the development of non-destructive methods for TSV characterization and evaluate the reliability and consistency of these approaches. Sandia National Laboratories, a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government. Figure 1

Copper-silicon carbide composite plating for inhibiting the extrusion of through silicon via (TSV)

For 3D packaging using TSV technology, it is required various techniques such as forming via holes on a wafer, filling conductive materials and interpretation of TSV reliability etc. Among them, solving the issue of reliability are standing out as a big problem for reaching commercialization in the future. When the conductive material filled in the TSV is expanded by the high-temperature process during the packaging process, it breaks the insulating layer and the metal interconnection which exist on via hole by extruding from the surface of the Si wafer. In this study, in order to suppress the Cu extrusion, electroplating was attempted by adding silicon carbide powder having almost no difference in thermal expansion coefficient with the Si chip in the Cu electroplating solution. As a result, the extrusion height of Cu-SiC was about 164 nm that is a height corresponding to 14.6% of the extrusion height of Cu. This is considered to be the result of extremely effectively suppressing the extrusion phenomenon after annealing by adding SiC powder with a low coefficient of thermal expansion into the conventional Cu plating solution.

Microsystems using three-dimensional integration and TSV technologies: Fundamentals and applications

As a powerful enabling technology, three-dimensional (3D) integration, which uses wafer bonding to integrate multiple wafers in the vertical direction and uses through‑silicon-vias (TSV) to electrically connect the wafers, have greatly promoted the technological advances and market development of MEMS in the past ten years. 3D integration enables heterogeneous integration of MEMS and IC chips fabricated with different technologies and materials, and thus permits the realization of integrated, sophisticated, and multifunctional microsystems with high performance, low cost, and compact size. This paper first introduces the fundamental fabrication technologies of 3D integration, and then reviews the recent progresses of MEMS and microsystems using 3D integration and TSV technologies. MEMS-CMOS integration, TSV-based wafer level packaging, 2.5D interposer integration of MEMS are illustrated with academic achievements and commercial products by functional categorization. Finally the conclusions are made and the future trends are discussed. © 2008 Elsevier B.V. All rights reserved.

A high-pass filter based on through-silicon via (TSV)

A fourth-order high-pass filter is proposed, which is formed by spiral inductors and TSV capacitors. The components of this filter rely on the TSV technology, which is generally regarded as vertical interconnection but now used to compose capacitor. The comparison of the results between finite element method and equivalent electric circuit obviously proves that they have nearly equal filtering characteristics including cut-off frequency and roll-drop rate. Moreover, the comparisons are made among the HPFs based on different technologies, and the challenges the proposed HPF faces are discussed.

Development of Eccentric Spin Coating of Polymer Liner for Low-Temperature TSV Technology With Ultra-Fine Diameter

Through-silicon-vias (TSVs) with a diameter of $3~\mu \text{m}$ and high aspect ratio of 15 are successfully fabricated based on a low-cost and low-temperature process involving spin coating of polyimide liner, electroless plating of Ni barrier/seed layer, and electroplating of Cu, which is suitable for via-middle/via-last processes that have a more stringent thermal budget. A novel eccentric spin coating technique is proposed for liner formation, which greatly improves the wafer-level uniformity and reduces the bottom dielectric thickness of the vias located close to the center of the wafer. The measured results show that the fabricated TSVs exhibit low depletion capacitance of 33 fF, low leakage current of 2.2 pA at 20 V, and good barrier property against Cu diffusion even after annealing at 400°C, indicating the feasibility of the proposed technique in high density and low area penalty 3-D large-scale integrated circuits.

Electrical models of through silicon Vias and silicon‐based devices for millimeter‐wave application

As the short vertical interconnections can significantly shorten the interconnect length between different circuits, three-dimensional integrated circuits (3D ICs) based on the through-silicon via (TSV) technology are considered as one of the most promising alternatives to overcome the scaling limits of Moore's low. Moreover, as the silicon technologies have been progressively expanded into the millimeter-wave (mmW) realm, the TSV technology also provides a promising option to realize a compact system with high performance and operating frequencies. This article provides an overview of recent advances in the development of TSV technologies and silicon-based passive devices for mmW applications. As various kinds of TSV losses are detrimental to the electrical performance of 3D ICs, especially in mmW systems, TSVs exploiting novel structures and materials still needs much more research, making it possible to integrate the passive device on 3D ICs and providing a promising option to realize a compact mmW system with excellent electrical performance and system reliability.

TSV Technology and High-Energy Heavy Ions Radiation Impact Review

Three-dimensional integrated circuits (3D IC) based on TSV (Through Silicon Via) technology is the latest packaging technology with the smallest size and quality. As a result, it can effectively reduce parasitic effects, improve work efficiency, reduce the power consumption of the chip, and so on. TSV-based silicon interposers have been applied in the ground environment. In order to meet the miniaturization, high performance and low-cost requirements of aerospace equipment, the adapter substrate is a better choice. However, the transfer substrate, as an important part of 3D integrated circuits, may accumulate charge due to heavy ion irradiation and further reduce the performance of the entire chip package in harsh space radiation environment or cause it to fail completely. Little research has been carried out until now. This article summarizes the research methods and conclusions of the research on silicon interposers and TSV technology in recent years, as well as the influence of high-energy heavy ions on semiconductor devices. Based on this, a series of research methods to study the effect of high-energy heavy ions on TSV and silicon adapter plates is proposed.