Through Silicon Via Structure Research Articles

FSI implications of EMC rheological properties to 3D IC with TSV structures during plastic encapsulation process

In this paper, an efficient numerical approach has been adopted to analyze the fluid/structure interaction (FSI) implications to 3D IC with through-silicon via (TSV) structures during plastic encapsulation process, under the effect of different EMC rheological properties. A simultaneous or direct solution procedure is employed to solve the solution variables of fluid/structural domain together. Therefore, this approach can provide better visualization of the actual plastic encapsulation process by considering FSI phenomenon during the process. Different epoxy molding compound (EMC) rheological properties have resulted dissimilar fluid flow characteristics, pressure distribution, air void entrapment level, structural displacement and von Mises stress, which are discussed in the paper. Unfavorable results are obtained when higher viscous flow takes place. EMC flow front prediction has been validated with the experimental results from literature. The numerical approach and results presented in this paper are able to provide useful information for the works in optimizing plastic encapsulation process.

Three-Dimensional Coaxial Through-Silicon-Via (TSV) Design

Being one of the most attractive 3-D integration solutions, through-silicon-vias (TSVs) electrically connect multiple strata of integrated circuits and/or devices in a vertical fashion. This paper examines the electrical performance of coaxial TSV, which is a new configuration that offers better signal integrity than other TSV structures. Various processing materials and physical geometries are considered for coaxial TSV designs. The full-wave extraction and empirical calculations show good agreement in TSV passive elements (RLGC). Latency, power, and crosstalk are evaluated and compared between coaxial TSVs and common signal-ground (S-G) paired TSVs. Furthermore, a wideband SPICE model is established to well fit the coaxial TSV fullwave solution, facilitating 3-D system design and evaluation.

Measurement and analysis of thermal stresses in 3D integrated structures containing through-silicon-vias

Three-dimensional (3-D) integration with through-silicon-vias (TSVs) has emerged as an effective approach to overcome the wiring limit beyond the 32nm technology node. Due to the mismatch of thermal expansion between the via material and Si, thermal stresses ubiquitously exist in the integrated 3-D structures. The thermal stresses can be significant to raise serious reliability issues, such as TSV extrusion and mobility degradation of logic devices. To understand the characteristics of the thermal stresses in TSVs, experimental measurements and numerical analysis are presented in this work. A precision wafer curvature technique was used together with micro-Raman spectroscopy to form a complementary approach to characterize the deformation and stresses in the TSV structures. The microstructures of the Cu vias were analyzed to provide insights to the deformation mechanisms. Guided by the experimental observations, finite element analysis was performed to analyze the thermal stresses taking into account the elastic anisotropy of Si and the plasticity of Cu. It was found that plastic deformation is localized within the Cu vias near the via/Si interface and may play an important role in TSV extrusion. Finally, the effect of thermal stresses on carrier mobility was investigated to evaluate the keep-out zone (KOZ) for logic devices near the TSVs.

Thermal Stresses of Through Silicon Vias and Si Chips in Three Dimensional System in Package

Thermal conduction and mechanical stresses in through silicon via (TSV) structures in three dimensional system in package (3D SiP) under device operation condition were discussed. A large scale simulator, ADVENTURECluster® based on finite element method (FEM) was used to simulate the effects of voids formed inside Cu TSVs on the thermal conduction and mechanical stresses in the TSV structure. The thermal performance that was required in 3D SiP was estimated to ensure the reliability. Simulations for thermal stresses in the TSV structure in 3D SiP were carried out under thermal condition due to power ON/OFF of device. In case that void was not present inside the TSV, the stresses in TSV were close to the hydrostatic pressure and the magnitude of the equivalent stress was lower than the yield stress of copper. Maximum principal stress of the Si chip in the TSV structure for the case without voids was lower than that of the bending strength of silicon. However, the level of the stresses in the Si chips should not be negligible for damages to Si chips. In case that void was present inside the TSV, stress concentration was occurred around the void in the TSV. The magnitude of the equivalent stress in the TSV was lower than the yield stress of copper. The magnitude of the maximum principal stress of the Si chip was lower than that of the bending strength of silicon. However, its level should not be negligible for damages to TSVs and Si chips. The stress on inner surfaces of Si chip was slightly reduced due to the presence of a void in the TSV.

Effect of Thermal Stresses on Carrier Mobility and Keep-Out Zone Around Through-Silicon Vias for 3-D Integration

Three-dimensional (3-D) integration with through-silicon vias (TSVs) has emerged as an effective solution to overcome the wiring limit imposed on device density and performance. However, thermal stresses induced in the TSV structures can affect the device performance by degrading carrier mobility and raise serious reliability concerns. In this paper, the effect of thermal stresses in TSV structures on carrier mobility and keep-out zone (KOZ) was investigated by focusing on the characteristics of the stresses near the surface where the electronic devices are located. The near-surface stresses were characterized by finite element analysis, and the stress effect on carrier mobility was evaluated by considering the piezoresistivity effect near the Si surface. In this paper, the elastic anisotropy of Si was taken into account to evaluate the effect on carrier mobility for both n- and p-channel MOSFET devices aligned along the [100] and [110] directions. The results showed a significant stress effect on carrier mobility, particularly for n-type Si with [100] device alignment and p-type Si with [110] device alignment. Based on these results, the dimension of the KOZ was estimated based on a criterion of 5% change in the carrier mobility. Finally, the effects due to stress interactions in a TSV array and plasticity in Cu vias on the KOZ were investigated. The effect of stress interaction was found to depend on the ratio of the pitch to diameter of the TSV array. When this ratio is less than 5, the stress interaction can increase the size of the KOZ. In contrast, the via material plasticity was found to be useful in reducing the stress level and hence the size of the KOZ.

RF-MEMS switch with through-silicon via by the molten solder ejection method

A radio frequency-microelectromechanical system (RF-MEMS) switch with through-silicon via (TSV) technology for hermetic packaging was designed and developed using the molten solder ejection method (MSEM). High frequency simulation was used to determine the lowest loss of the shift-aligned ground-signal-ground (GSG) TSV structure. The RF-MEMS with shift-aligned TSV was successfully developed by integrating surface micromachining with MSEM. The electrical properties of RF-MEMS switches with the shift-aligned TSV were measured, and a low insertion loss of 0.1dB at 15GHz was achieved for a GSG TSV configuration.

Through Silicon Via Fabrication with Low-κ Dielectric Liner and Its Implications on Parasitic Capacitance and Leakage Current

Through silicon via (TSV) has emerged as an essential enabler for three-dimensional integrated circuit (3D IC). The basic TSV structure consisting of a via hole in the Si substrate filled with metal such as copper and lined with a dielectric liner, forms a metal–oxide–silicon (MOS) capacitor structure. To benefit the performance of 3D IC, the TSV used to interconnect vertically stacked dies must introduce small electrical parasitic, such as capacitance. The isolation property of the dielectric liner must also be preserved to control the leakage current. In this work, TSV with acceptable sidewall roughness is achieved and lined with low-κ material with an effective dielectric constant of ∼2.8. Low-κ liner with conformal step coverage is successfully achieved in our fabrication process. Based on electrical measurement, it is found that the integration of the low-κ liner reduces the TSV capacitance by ∼27.6% as compared with the conventional plasma-enhanced tetraethylorthosilicate (PETEOS) oxide liner. In addition, current–voltage (I–V) measurement is carried out to monitor and study the leakage of the low-κ liner. No abrupt breakdown is observed until at least at an electric field of 3 MV/cm which corresponds to 60 V. Annealing of the TSV structure in forming gas (N2/H2) at 350 °C for 30 min successfully reduces the leakage current density by ∼1.6×, to a mid-distribution value of ∼6.8×10-6 A/cm2.

Micro-Raman spectroscopy and analysis of near-surface stresses in silicon around through-silicon vias for three-dimensional interconnects

Three-dimensional integration with through-silicon vias (TSVs) has emerged as an effective solution to overcome the wiring limit imposed on device density and performance. However, thermal stresses induced in TSV structures raise serious thermomechanical reliability concerns. In this paper, we analyze the near-surface stress distribution in a TSV structure based on a semi-analytic approach and finite element method, in comparison with micro-Raman measurements. In particular, the depth dependence of the stress distribution and the effect of elastic anisotropy of Si are illustrated to properly interpret the Raman data. The effects of the surface oxide layer and metal plasticity of the via material on the stress and Raman measurements are discussed. The near-surface stress characteristics revealed by the modeling and Raman measurements are important for design of TSV structures and device integration.

GHz High Frequency TSV for 2.5D IC Packaging

TSV (Through Silicon Via) is the key enabling technology for 2.5D & 3D IC stacking solution in FCBGA (Flip Chip Ball Grid Array). As the 2.5D interposer design pushing toward smaller & shorter via due to high I/O density and high frequency requirement, the electrical performance of thinner interposer is therefore much more challenging in low signal loss performance for high frequency application and process. From the structure point of view, the silicon interposer is an additive layer between top side chip(s) and bottom side substrate, it is therefore an additional electrical interconnection which affects the signal propagation between chip(s) and substrate. Therefore, the performance of the TSV insertion loss in silicon interposer becomes critical, especially for above GHz application. Real measurement is conducted to validate the electrical performance of TSV interconnection up to 67GHz, and the wideband scalable model of TSV is also proposed and compared with the measured data. The measurement of this TSV structure has demonstrated the advantages with low parasitic capacitance and low insertion loss at high frequency. Full validated reliability test is also presented to verify interposer fabrication, assembly process optimization, and interconnection stability of the 2.5D IC package.

A Novel Wafer-Level Double Side Packaging and Its Microwave Performance

In this paper, a wafer-level System-in-Packaging structure using through silicon via (TSV) for integration on both sides of the silicon wafer is presented. It is composed of BCB/ metal multilayers, high-resistivity silicon substrate with TSV. To reduce the transmission loss in microwave frequency, not only the high-resistivity silicon is used, but also a special TSV structure with 6 grounded shielding vias around the core via are adopted. Microstrip line (MSL) is used to transmit high-frequency signal on package plane together with the low permittivity intermediate dielectric polymer, BCB. Descriptions on the interconnection structure and the fabrication process are included. The microwave measurement result of the MSL connected by TSVs is measured up to 35GHz. The results of both the simulation and the measurement are presented.

Electrical Performance of Through-Silicon Vias (TSVs) for High-Frequency 3D IC Integration Applications

In this study, the electrical performance of a general TSV structure for high-frequency 3D IC integration applications is investigated. Emphasis is placed on the proposal of an analytical model and the analytical equations of a TSV with all its key parameters. Also, the model and equations are verified, both in the frequency and time domains, by more detailed finite element analyses. Finally, a TSV electrical design guideline is proposed.

Thermal expansion behavior of through-silicon-via structures in three-dimensional microelectronic packaging

Thermo-mechanical reliability is an important issue for the development and deployment of the through-silicon-via (TSV) technology in three-dimensional (3D) microelectronic packaging. The mismatch in coefficient of thermal expansion (CTE) between the array of copper (Cu) lines and the surrounding silicon (Si), upon temperature variation, affects the overall thermal expansion behavior of the whole TSV structure itself and generates an internal stress state. In this work we use the finite element method to numerically study the effective in-plane CTE of the Si/Cu composite structure. A 3D unit-cell approach is undertaken, which takes into account uniformly distributed TSVs in the Si chip. Results of the temperature-dependent effective CTE can be used as model input for simulating larger-scale 3D packages where the Si/Cu TSV structure is treated as a homogeneous material. We also examine the evolution of stress and deformation fields, and identify potential reliability concerns associated with the thermal loading.

Assessment and Characterization of Stress Induced by Via-First TSV Technology

Through silicon via (TSV) is a key enabling technology for 3D stacking. One of the main concerns regarding the TSV introduction inside the IC fabrication is the resulting stress buildup in the silicon substrate that may induce warpage or expansion at the wafer level, strain and crystalline defects in the neighboring silicon of the TSV, and finally can impact the performance and reliability of the CMOS devices as well. Polysilicon, tungsten, and copper are the three main conductors that are currently considered for TSV fabrication. In the first part of this paper, the different factors that contribute to the stress in these three TSV types, including the geometry, the materials, and the process, will be reviewed. After bonding on a temporary carrier and thinning of the substrate to expose the via, the stress built up during the fabrication of the TSV can be also revealed by the expansion of the silicon membrane. We present thermomechanical FEM simulations and compare them with the experimental findings. We also present some characterizations of silicon defects by chemical revelation around the TSV structures. For characterization of the stress in TSV structures, different techniques as EBSD, microRaman, and XRD are presented. Finally, we conclude that with the optimization of some key processing steps, the stress induced in via-first technology may be acceptable for IC integration.

Influence of Bosch Etch Process on Electrical Isolation of TSV Structures

Bosch process is widely used in the fabrication of through silicon via (TSV) holes for 3-D integrated circuit and 3-D Packaging applications mainly due to its high silicon etch rate and selectivity to mask. However, the adverse impact on the electrical performance of the TSV due to the sidewall scallops or wavy profile due to the cyclical nature of the Bosch process has not been thoroughly investigated. This paper therefore focuses on the impact of sidewall scallops on the inter-via electrical leakage performance. Based on finite element analysis, this paper describes that the high stress concentration on the dielectric and barrier layers at the sharp scallops can potentially contribute to barrier failure. It is demonstrated that by smoothening the sidewalls of the TSV, the thermo-mechanical stresses on the dielectric and tantalum barrier is significantly reduced. A test vehicle is designed and fabricated with different geometry of deep silicon vias to study the impact of sidewall profile smoothening for different copper diffusion barrier stacks. It is experimentally demonstrated that the inter-via electrical leakage current can be reduced by almost three orders of magnitude when the sidewall roughness is reduced or replaced by a smoother sidewall. It is also indicated that it is sufficient to smoothen the initial few micrometers of the TSV depth by using a non-Bosch etch process. It is concluded that the Bosch etch process can still be used, with all its merits of high etch rate and high etch selectivity, by tailoring a short initial etch step to smoothen the top sidewalls to minimize the adverse effects of the sidewall scallops.

Investigation of durability of TSV interconnect by numerical thermal fatigue analysis

3D packaging using through silicon via (TSV) technology is becoming important in IC packaging industry. However, increased number of interconnects and extreme miniaturization suggest that thermo-mechanical reliability and fatigue will aggravate. In traditional package, thermo-mechanical fatigue failure mostly occurs as a result of damage in the solder joint. In TSV technology, however, the driving failure may be the TSV via or TSV interconnects. In this study, the durability of TSV technology is investigated using finite element method. Thermal fatigue phenomenon due to the plastic strain caused by repetitive temperature cycling is analyzed, and possible failure locations are discussed. In particular, the effects of via size, underfill material, and via filling material on the thermal fatigue reliability are investigated. The expected fatigue life indicates that the presence of underfill material is essential in improving the durability of the TSV structure. The plastic strain increases with the via size increases, therefore the thermal fatigue life increases as the via size decreases. For different via filling materials such as copper, nickel and tungsten, amount of plastic strain is very similar, suggesting that nickel could be used for via filling material. However, the locations of the maximum strain are different for each filling material.

3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias

In this paper, we report on the processing and the electrical characterization of a 3-D-wafer level packaging through-silicon-via (TSV) flow, using a polymer-isolated, Cu-filled TSV, realized on thinned wafers bonded to temporary carriers. A Cu/Sn micro-bump structure is integrated in the TSV process flow and used for realizing a two-die stack. Before TSV processing, the Si wafers are bonded to temporary carriers and thinned down to 50 μm. The actual TSV and micro-bump process uses 3 masks, two Si-deep-reactive ion etching steps and a polymer liner as a dielectric. The dimensions of the TSV structure are: 35 μm OTSV, 5 μm thick polymer liner, 25-μm-O Cu TSV, 50 μm deep TSV, and a 60 μm TSV pitch.

CMP process development for the via-middle 3D TSV applications at 28nm technology node

A through-silicon-via (TSV) chemical mechanical polishing (CMP) process with three polishing steps, including Cu polishing, Cu barrier/isolation layers polishing and dielectric SiN stop layer polishing, has been proposed to form the [email protected] deep with [email protected] diameter size via-middle TSV structures at 28nm technology node. The integrated process optimizations of pre-TSV CMP anneal and electrochemical deposition (ECD) of Cu have been evaluated to enlarge TSV CMP process window and prevent the formations of the Cu extrusion and voids post-back-end-of-line (BEOL) processes. Less than 150A of within wafer and within lot inter-layer dielectric (ILD) mapping thickness range control and less than 100A Cu extrusion level without voids post-TSV capping layer deposition can be achieved as implementing 400^oC for 10min pre-TSV CMP annealing condition and uniform TSV ECD profile electroplated in less impurity chemical solution.

Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon Vias for 3-D Interconnects

Continual scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, 3-D integration with through-silicon vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Among others, thermomechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper examines the effects of thermally induced stresses on the interfacial reliability of TSV structures. First, 3-D distribution of the thermal stress near the TSV and the wafer surface is analyzed. Using a linear superposition method, a semianalytic solution is developed for a simplified structure consisting of a single TSV embedded in a silicon (Si) wafer. The solution is verified for relatively thick wafers by comparing to numerical results from finite element analysis (FEA). The stress analysis suggests interfacial delamination as a potential failure mechanism for the TSV structure. An analytical solution is then obtained for the steady-state energy release rate as the upper bound for the interfacial fracture driving force, while the effect of crack length is evaluated numerically by FEA. With these results, the effects of the TSV dimensions (e.g., via diameter and wafer thickness) on the interfacial reliability are elucidated. Furthermore, the effects of via material properties and dielectric buffer layers are discussed.

Fast and Accurate Analytical Modeling of Through-Silicon-Via Capacitive Coupling

In this paper, we present analytical models for fast estimation of coupling capacitance of square-shaped through-silicon vias (TSVs) in three-dimensional integrated circuits (3D ICs). Errors between our model and Synopsys Raphael simulation on regular TSV structures remain less than 6.03% while the computation time of our model for capacitance estimation is negligible. We also develop a simple capacitance estimation technique to extract TSV-to-TSV coupling capacitance in general layouts. Average errors between our model and Raphael simulation on random TSV structures is 5.06%-8.24%, and maximum errors remain less than 18.91% which is tolerable for fast capacitance estimation in computer-aided design area.

Strain Gradient Finite Element Analysis of Size Dependence of Thermal Stresses in Through-Silicon Vias (TSVs)

Through-Silicon Vias (TSVs) technology, which is widely used in three-dimensional (3D) Microsystems packaging, has been investigated by using a strain gradient finite element method (FEM). A thermomechanical strain gradient constitutive law was embedded into the commercial software ABAQUS to consider the size dependence of thermal stresses in TSVs. Our numerical results show that when both thicknesses of SiO2 dielectric layer and Si substrate are kept to a constant, for a given via depth/radius ratio, the Mises stress decreases with the decrease in the radius above 100 nm, and then it increases markedly with the further decrease in the via radius below 100 nm, which is not consistent with the results obtained by the conventional FEM. It is also shown that as the whole size of the TSV structures is scaled down proportionally, for a given via depth/radius ratio, the peak Mises stresses are almost size scale- independent above 100 nm and exhibit a strong size scale effect below 100 nm.