Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon Vias for 3-D Interconnects

Abstract

Continual scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, 3-D integration with through-silicon vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Among others, thermomechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper examines the effects of thermally induced stresses on the interfacial reliability of TSV structures. First, 3-D distribution of the thermal stress near the TSV and the wafer surface is analyzed. Using a linear superposition method, a semianalytic solution is developed for a simplified structure consisting of a single TSV embedded in a silicon (Si) wafer. The solution is verified for relatively thick wafers by comparing to numerical results from finite element analysis (FEA). The stress analysis suggests interfacial delamination as a potential failure mechanism for the TSV structure. An analytical solution is then obtained for the steady-state energy release rate as the upper bound for the interfacial fracture driving force, while the effect of crack length is evaluated numerically by FEA. With these results, the effects of the TSV dimensions (e.g., via diameter and wafer thickness) on the interfacial reliability are elucidated. Furthermore, the effects of via material properties and dielectric buffer layers are discussed.