Abstract
TSV (Through Silicon Via) is the key enabling technology for 2.5D & 3D IC stacking solution in FCBGA (Flip Chip Ball Grid Array). As the 2.5D interposer design pushing toward smaller & shorter via due to high I/O density and high frequency requirement, the electrical performance of thinner interposer is therefore much more challenging in low signal loss performance for high frequency application and process. From the structure point of view, the silicon interposer is an additive layer between top side chip(s) and bottom side substrate, it is therefore an additional electrical interconnection which affects the signal propagation between chip(s) and substrate. Therefore, the performance of the TSV insertion loss in silicon interposer becomes critical, especially for above GHz application. Real measurement is conducted to validate the electrical performance of TSV interconnection up to 67GHz, and the wideband scalable model of TSV is also proposed and compared with the measured data. The measurement of this TSV structure has demonstrated the advantages with low parasitic capacitance and low insertion loss at high frequency. Full validated reliability test is also presented to verify interposer fabrication, assembly process optimization, and interconnection stability of the 2.5D IC package.
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