Abstract

Through-Silicon Vias (TSVs) technology, which is widely used in three-dimensional (3D) Microsystems packaging, has been investigated by using a strain gradient finite element method (FEM). A thermomechanical strain gradient constitutive law was embedded into the commercial software ABAQUS to consider the size dependence of thermal stresses in TSVs. Our numerical results show that when both thicknesses of SiO2 dielectric layer and Si substrate are kept to a constant, for a given via depth/radius ratio, the Mises stress decreases with the decrease in the radius above 100 nm, and then it increases markedly with the further decrease in the via radius below 100 nm, which is not consistent with the results obtained by the conventional FEM. It is also shown that as the whole size of the TSV structures is scaled down proportionally, for a given via depth/radius ratio, the peak Mises stresses are almost size scale- independent above 100 nm and exhibit a strong size scale effect below 100 nm.

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