Through Silicon Via Interconnects Research Articles

Analytical and Measurement-Based Method for Diagnosing the Fault of Channels in TSV-Based 3D ICs

Three-dimensional integrated circuits (3D ICs) based on through silicon via (TSV) technology can effectively solve many bottlenecks in the development of ICs. It has rapidly developed into a key cutting-edge technology representing the medium and long-term sustainable development of microelectronics industry. Process fluctuation causes TSV process defects, resulting in the change of structural parameters of RDL and TSV interconnection structure. Finally, it leads to the degradation of performance parameters and functional failure of 3D interconnection and devices. Aiming at the high-resistance and open-circuited faults of 3D ICs, this paper develops an analysis method based on micro nano machining and detection technology. The electrical characteristics and images of typical chain TSV interconnections are analyzed by scanning electron microscope high-resolution imaging. The mechanism of fault diagnosis is based on potential difference and electron transfer.

Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)

Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bumpless interconnects between wafers and between chips and wafers are a second-generation alternative to the use of micro-bumps for WOW and COW technologies. WOW and COW technologies for BBCube can be used for homogeneous and heterogeneous 3DI, respectively. Ultra-thinning of wafers down to 4 μm offers the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of Through-Silicon-Vias (TSVs). Bumpless interconnect technology can increase the number of TSVs per chip due to the finer TSV pitch and the lower impedance of bumpless TSV interconnects. In addition, high-density TSV interconnects with a short length provide the highest thermal dissipation from high-temperature devices such as CPUs and GPUs. This paper describes the process platform for BBCube WOW and COW technologies and BBCube DRAMs with high speed and low IO buffer power by enhancing parallelism and increasing yield by using a vertically replaceable memory block architecture, and also presents a comparison of thermal characteristics in 3D structures constructed with micro-bumps and BBCube.

A RF Redundant TSV Interconnection for High Resistance Si Interposer.

Through Silicon Via (TSV) technology is capable meeting effective, compact, high density, high integration, and high-performance requirements. In high-frequency applications, with the rapid development of 5G and millimeter-wave radar, the TSV interposer will become a competitive choice for radio frequency system-in-package (RF SIP) substrates. This paper presents a redundant TSV interconnect design for high resistivity Si interposers for millimeter-wave applications. To verify its feasibility, a set of test structures capable of working at millimeter waves are designed, which are composed of three pieces of CPW (coplanar waveguide) lines connected by single TSV, dual redundant TSV, and quad redundant TSV interconnects. First, HFSS software is used for modeling and simulation, then, a modified equivalent circuit model is established to analysis the effect of the redundant TSVs on the high-frequency transmission performance to solidify the HFSS based simulation. At the same time, a failure simulation was carried out and results prove that redundant TSV can still work normally at 44 GHz frequency when failure occurs. Using the developed TSV process, the sample is then fabricated and tested. Using L-2L de-embedding method to extract S-parameters of the TSV interconnection. The insertion loss of dual and quad redundant TSVs are 0.19 dB and 0.46 dB at 40 GHz, respectively.

Performance evaluation of noise coupling on Germanium based TSV filled material for future IC integration technique

• Due to its CTE mismatch and Electromigration (EM) issues of Cu as TSV, Germanium can be used as an alternative material. • Quantum-well (QW) formed between Silicon substrate and Germanium core can be used as a high-speed TSV interconnect. • It opens up the window towards the future IC Integration (3D IC). 3D IC Integration shows the most emerging technology for future integration nodes which is now a most important trend for the semiconductor industries. Through-silicon-via (TSV) based integration is the prime technique to facilitate 3D IC integration without compromising the Moore’s law. It is likely to usher the IC industries a paradigm shift from planar integration as it provides major benefits like improvement of system performance, power and enables heterogeneous integration. In this paper, we report Germanium/poly-germanium as an substitute material for Silicon/poly-silicon due to its superior carrier mobility. Mobility of electrons and holes in c-Silicon is 1500 cm 2 /V-s and 450 cm 2 /V-s respectively, where as in c-Germanium, the respective values are 3900 cm 2 /V-s and 1900 cm 2 /V-s. Therefore, considering these carrier mobility values we can envisage that poly germanium will be one of the ideal candidate towards realizing a high speed TSV interconnect when compared with poly-silicon. Nevertheless, even though copper is used widely to fill TSVs, it is also bereft of proper thermal expansion match with Silicon/dielectric (SiO 2 ). The coefficient of thermal expansion (CTE) of Cu (∼17.5x 10 -6 /°C) is many times more than of silicon (∼2.5x 10 -6 /°C). Hence, there will be heavy mismatch between Cu filled TSV and Silicon/SiO 2 , and then it creates stress and strain between the interfaces. The CTE of germanium (5.8x 10–6/°C) is very close to Silicon, thus there CTE mismatch is very less, this fact is also an added advantage for Germanium to challenge copper as TSV material.

Optical Beam-Based Defect Localization Methodologies for Open and Short Failures in Micrometer-Scale 3-D TSV Interconnects

We report laser-based fault isolation methodologies for the localization of open and short failures in $1 \times 5\,\,\mu \text{m}$ via-last through-silicon via (TSV) structures for 3-D system-on-chip (SoC) integration. Due to the photosensitive TSV interconnect capacitance, observation of the photocapacitance response enables nondestructive localization of metallization ruptures. A light-induced capacitance alteration (LICA) measurement is demonstrated on an open failed $1 \times 5\,\,\mu \text{m}$ TSV chain structure with a manufacturing defect. We validate our measurements with active voltage contrast imaging in the scanning electron microscope (SEM) and focused-ion beam (FIB) cross sectioning. Second, TSV dielectric defects generating leakage current between TSV and substrate (i.e., short defects) are detected and localized by sensing the laser-induced TSV photocurrent. An optical beam-induced current (OBIC) measurement is demonstrated on electrically overstressed TSV array structures whereby multiple TSVs are configured in a parallel arrangement. By applying a selective substrate removal process, we can expose the full TSV array and perform optical and tilted SEM inspection and reveal pinhole defects in the TSV liner. We further investigate the effect of breakdown energy on the pinhole formation, relate electrical measurements to SEM inspection, and confirm our results by FIB cross sectioning.

Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment

The vertical interconnects between the components of a 3D system-on-chip (SoC) are realized by through-silicon vias (TSVs). These large global vias are a frequent performance bottleneck due to their high capacitive crosstalk. In order to reduce it, this work analyses the effect of temporal misalignment between the transitions on the signal nets of an interconnect structure and presents a technique to exploit it. The approach, based on a crosstalk-aware net-to-TSV assignment and hardware-efficient low-power codes, enables a dramatic improvement in the 3D interconnect performance. Circuit simulations show that the proposed technique reduces the delay and the noise of modern TSV interconnects by about 35%–50%, without noticeable cost. In combination with the classical bus invert coding, an additional decrease in the energy consumption by about 17% is obtained.

Fabrication and RF Property Evaluation of High-Resistivity Si Interposer for 2.5-D/3-D Heterogeneous Integration of RF Devices

In this paper, a high-resistivity silicon (HR-Si) interposer integrated with through-silicon via (TSV) electrically grounded coplanar waveguide (CPW) line is presented for 2.5-D/3-D heterogeneous integration of radio frequency (RF) microelectronics devices. In addition, design of TSV interconnection composed of two coaxial ladder-hollow-annular Cu (copper) TSVs of different diameters is utilized to maintain a sufficient freedom for strict standard cleaning to avoid Si resistivity degradation. The formation of the coaxial ladder TSV structure is more beneficial to the subsequent plating process because it reduces the aspect ratio of TSV vias. Hollow-annular Cu TSV is manufactured in order to reduce the problem of mismatch in coefficient of thermal expansion among TSV’s constituent materials. A layer of Au (aurum) film is utilized to passivate the exposed Cu surface of Si interposer. Au is widely used in III–V groups’ devices because of the good compatibility with photonic integrated circuits, conductivity, and corrosion resistance. HR-Si interposer with TSV grounded CPW line and test structure is fabricated and characterized. With the monitoring test results, it can be found that it changes little in the resistivity of Si substrate, though the whole process, which is a basic requirement for RF performance. RF property test results show that the insertion loss is about −0.20 dB/mm at 10 GHz for the presented TSV grounded CPW line and −0.02 dB per TSV. These test results are better than the traditional design. To verify its applicability to 2.5-D/3-D heterogeneous integration, RF microelectronics die is assembled on TSV interposer and tested, and the test results prove that it works properly.

Pulse Electrodeposition of Cu through-Silicon-Via (TSV) with Surface Suppressor

In recent years, many researches have been focused on the miniaturization of the integrated circuit (IC) feature size to improve the performance of semiconductor devices. However, we are facing the problems such as physical limit of the miniaturization and then increasing processing cost. To overcome these problems the Through-Si-Via (TSV) interconnection, a kind of the 3D interconnection, is a promising technology that could achieve high density, lower energy consumption and high performance in the IC. Since the TSV filling process is costly in the entire TSV process, the TSV filling process which the Cu electrodeposition for TSV is one of key processes. The TSV bottom-up filling which the filling of Cu from the bottom to the top of via with suppressed lateral growth is the solution to ensure a void free filling in high aspect ratio TSV. The bottom-up filling could be achieved by using additives like a suppressor and an accelerator in the electrolyte. In a theoretical model, the suppression breakdown at the bottom of TSV cause the bottom-up filling of TSV. Simultaneous desorption of suppressor by high potential due to ion depletion in the via bottom leads focus of current at the via bottom. Due to adsorption/desorption behavior of the suppressor, the bottom-up TSV filling could be achieved by only using the suppressor.1-3 Furthermore, it was reported that the suppressor at the sidewall is replaced by the accelerator and then the bottom-up filling performance was degraded.3 Lu et al. introduced the nanotwin Cu thin film, which had been attained with pulse electrodeposition.4 Mechanical properties of the Cu thin film is significantly enhanced by highly dense coherent twin boundaries without the degradation of electrical conductivity. Because it could effectively block the dislocation motion without interrupting the migration of electrons.4 The mechanical property of TSV interconnection such as thermal behavior is important as well as the electrical property including electrical conductivity for improvement TSV performance. Therefore, the nanotwin Cu is proper for the TSV interconnection. In this study, nanotwin Cu was applied to fill into high aspect ratio of via (diameter = 5 µm, depth = 60 µm) with pulse current conditions. The deposition condition between direct current and pulse current was compared to observe the filling characteristics. The mechanical properties as the thermal expansion behavior, which is critical to adopting integrated devices, of nanotwin Cu were investigated. As a result, the results with pulse current condition showed obvious improved the TSV filling property than direct current condition. 1. T. P. Moffat and D. Josell, J. Electrochem. Soc., 159, D208 (2012). 2. T. Moffat and D. Josell, Journal of The Electrochemical Society, 159, D208 (2012). 3. L. Yang, A. Radisic, J. Deconinck, and P. M. Vereeckena, J. Electrochem. soc., 160, D3051 (2013). 4. L. Lu, Science, 304, 422-426 (2004).

Machine-Learning Approach in Detection and Classification for Defects in TSV-Based 3-D IC

A through-silicon via (TSV) is a conducting copper nail, which provides an electrical connection through a substrate, and is expected to be used extensively to provide high-speed interconnects between the top and bottom of an active die. However, some TSV structural defects such as pinholes and voids are difficult to capture as they commonly affect TSV performance parameters rather than TSV logical function. In order to electrically detect failures, it is necessary to study and analyze electrical characteristics of defects in advance. Testing TSV interconnects for manufacturing defects poses major challenges, and new design-for-test techniques are needed. Here, a novel nondestructive defect detection method using machine learning (ML) is proposed in order to detect void, short, and open defects in TSV-based 3-D ICs. A supervised ML approach is used to build a classification model from training S-parameter data sets containing the defected TSV and the normal TSV. The performance of the random forest classifier is tested for various amounts of void, short, and open defects in TSV-based 3-D-stacked ICs with satisfactory results.

3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV)

This paper describes a four-layer-stacked chip with 45-nm dynamic random access memory (DRAM) dice and 65-nm logic controller, which are interconnected by backside-via-last through-silicon via (TSV) processes. Fabrication of backside-via-last process and multiple die stacking using chip-to-chip bonding are presented with electrical connection between TSV (5- $\mu \text{m}$ -diameter/50- $\mu \text{m}$ -length) and Cu interconnects. Excellent fabrication of stacked dice verified that the micro bumps with 12- $\mu \text{m}$ diameter are bonded using three step temperature bonding profile. Further stacked DRAM/Logic performance and system verifications are demonstrated successfully using 3-D heterogeneous integration.

Development of high-yield and high-reliability design for high-performance ultra large scale 3DLSI processor

With LSI micro-fabrication technology reaching its scaling limits, miniaturizing LSIs based on Moore's Law is unable to satisfy the CPU/memory module performance for high-speed, low-power, high-end servers, an alternative integration technology such as three-dimensional integration (3DI) is becoming mainstream. With the development of 3D stacked high-performance processors, specifications that excel in power consumption (200 to 300 W), heat generation, number of electrodes and large die area are required, necessitating a major technical leap from the conventional 3D packaging technologies. A guarantee of reliability and the yield loss is very severe, because of the high-performance processor's needing 30 times or more the both die area and the number of pins compared with the combinational high band width memory stacking. We were the first to verify 3D logic device operation by integrating the following technologies: through-silicon via (TSV) technologies, in which signals are connected in the shortest distance between a top and bottom stacked ultra-large die area processor die; novel redundancy signal transmission design technology; super multi-pins connection technology for high-yield signal transmission with high bandwidth; and high reliability solder joint materials considering power integrity (PI) between stacked dies. To achieve the high-yield TSV connection, the TSV redundant circuit was designed and installed into the stack dies due to the difficulty of the avoidance of defect density (D0) increasing such as large die area. Novel logic macro design with one redundant TSV for 16 signal node enabled the accurate switching selection to redundant defective TSV by using the execution of a pre-test sequence to find bad TSV. In addition, a redundant logic circuit of top and bottom interconnect is a design that gives control signal the redundancy. As a result, the higher operation guarantee was given to the operation execution of controlling circuit. This redundant circuit design technology demonstrated without yield loss of TSV interconnect. For high-reliability fine pitch bump (40-μm pitch) and 10-μm TSV interconnect formation technologies, a large-current, high-heat dissipation and high-precision stacking technology were required. We have developed a process technology for fine-pitch micro bump junctions supporting large current and high-precision I/O bumps stacking dies with 200,000 or more pins using by Ni-Sn intermetallic compound (IMC) solder materials. We also have developed a high accuracy of large die stacking process to be used in fine TSV in which large amounts of current flow and connection terminal sections on dies, achieving stable supply of 300-Watt-class power consumption. Compared with the current density for a 10-year guaranteed lifetime, the case of IMC alloy joining achieves a current density resistance of 4 times more than that of conventional Sn-Ag solder materials, and this has proven to be effective for a high-performance processor. By developing 3DLSI packaging technology compatible with ultra large dies for a high-performance processor and overcoming the issue of yield and reliability, we have achieved a redundancy design technology and micro bump materials of high-yield at product level stacked logic processor with over 750 mm square as full reticle shot size. In this paper, we will discuss the important key redundancy TSV design method and micro bump material technologies; in 3D packaging technology for realizing high-performance ultra large scale processor.

High Aspect Ratio through Silicon Via Filling By Nickel-Tungsten Alloy Using Graphene As a Conducting and Barrier Layer

Recently, three-dimensional (3D) chip stacking becomes more and more important because of “More than Moore” story. Through silicon via (TSV) technology is one approach to achieve the target of “more than Moore”. However, the coefficient of thermal expansion (CTE) of copper filled in the TSV may lead to failure of the TSV interconnects because the copper CTE is much higher than that of silicon. The packaging materials with different CTEs will induce large stress at interfaces of materials. To overcome this problem, we choose nickel to substitute copper as a filling material of TSV since the nickel CTE is lower than copper CTE. To further decrease the CTE of the filling material, a few tungsten whose CTE is similar to that of silicon is codeposited during filling plating. Graphene has drawn extensive attention due to its outstanding electrical and thermal properties. In addition, graphene can be used as a barrier layer of copper diffusion. Also, the CTE of graphene is similar to that of silicon. Hence, we use graphene to replace the TiN barrier layer and the copper seed layer, which was used in the traditional TSV process. The filling performance is evaluated by examining vertical cross-sections and top-down cross-section of the filled TSVs by using optical microscope (OM). The Ni-W pillar is examined by scanning electron microscopy (SEM). The thermal reliability of the fully filled TSV is evaluated after a thermal annealing process. The CTE of the filled Ni-W is measured by thermomechanical analysis.

Electrical Modeling and Analysis of a Mixed Carbon Nanotube Based Differential Through Silicon via in 3-D Integration

Based on the extracted equivalent parasitic parameters, the distributed transmission line model of a mixed carbon nanotube bundle (MCB) built signal-ground-signal-type differential through silicon via (TSV) is established and validated against the multiconductor transmission line model (MTL) results and predictive experiment results over a wide frequency range. Using the proposed model, the effect of various dimensional parameters and material properties on the signal loss and characteristic impedances of the differential TSV interconnect is investigated for odd- and even-mode signal propagation, respectively. It is observed that dielectric thickness is the most important factor affecting the transmission characteristics of TSV interconnects for the proposed TSV configuration. Moreover, various electrical performances of the proposed differential TSV, such as insertion loss, eye opening area, characteristic impedances, and 50% time delay are evaluated and compared to that of a signal-ground-type single ended TSV interconnect. The results presented in this paper will be helpful to fully understand the CNT-TSV electrical characterization and provide some signal integrity-aware guidelines for circuit designers in early planning stage.

Post-Bond Interconnect Test and Diagnosis for 3-D Memory Stacked on Logic

3-D stacked integrated circuit (IC) technology based on through-silicon vias (TSVs) provides numerous advantages as compared to traditional 2-D-ICs. A potential application is memory stacked on logic, providing enhanced throughput, and reduced latency and power consumption. However, testing the TSV interconnects between the two dies is challenging as both memory and logic dies might come from different providers. Currently, no standard exists and the proposed solutions fail to address dynamic and time-critical faults (at speed testing). In addition, memory vendors have not been in favor to put additional design-for-testability structures such as Joint Test Action Group for interconnect testing on their memory devices. This paper proposes a new memory-based interconnect test (MBIT) approach for 3-D memories stacked on logic (e.g., CPUs). A structural approach is used to develop fault models, their detection conditions, and test and diagnosis patterns. The test patterns are applied by read and write instructions to the memory and are validated by a case study where a 3-D memory is assumed to be stacked on a MIPS64 processor. The main benefits of the MBIT approach are: 1) zero area overhead; 2) the ability to detect both static and dynamic faults and perform at speed testing; 3) flexibility in applying any test pattern, as this can be executed by the CPU on the logic die; 4) extreme short test execution time; and 5) the ability to perform interconnect diagnosis.

Study on crosstalk characteristic of carbon nanotube through silicon vias for three dimensional integration

Coupling noise induced by through silicon vias (TSVs) is expected to be a major concern for three dimensional integrated circuits (3-D ICs) system design. Using equivalent electrical parameters for carbon nanotube (CNT) TSV interconnects, a lumped crosstalk noise model is introduced to capture the TSV-to-TSV coupling noise in CNT via based 3-D ICs and validated with multiple conductor transmission line (MTL) simulation results. The effect of geometrical and material parameters involved on the noise transfer function and peak crosstalk noise, such as insulation thickness, TSV–TSV spacing, TSV height, TSV radius, substrate conductivity and metallic CNT density, is investigated with the proposed model. Simulation results show that the TSV coupling can be divided into three frequency behavior regions. Three approaches using driver sizing, grounded vias shielding and air gap-based silicon-on-insulator (SOI) technique are proposed to mitigate TSV crosstalk coupling noise. The proposed approaches are demonstrated in frequency- and time- domain simulations. They provide the reduction in full-band noise transfer function by an average of 11.71dB, 24.85dB and 3.46dB, and the decrease in 1GHz peak noise voltage by 53.24mV, 40.72mV and 15.1mV.

Through Silicon via Filling by Electroplating Using Reduced Graphene Oxide (rGO) as a Conducting Layer

Graphene materials, including single layer and multi layer graphene platelet, have recently drawn extensive attention due to their outstanding electrical and thermal properties. Reduction of grapheme oxide (GO) is a method for preparing the graphene film. Since GO has a large amount of oxygen functional groups, it can be well dispersed in several solvents and enable it to be coated on a substrate by using a chemical grafting method[1].Three-dimensional (3D) chip stacking is a major focus in recent research and development of microelectronics, MEMS, and MOEMS technology. Through silicon vias (TSVs) play a key role in the 3D IC chip stacking connections. A main advantage of TSV is to make the shortest chip-to-chip vertical interconnection, which allows for size reduction of the chip and reducing signal transmission delay[2]. Electrodeposition plays an important role for TSV metallization, especially copper electrodeposition, which is a critical technology and generally used in the 3D chip packaging.For TSV technology, the thermo-mechanical fatigue may lead to failure in the TSV interconnects[3] because the coefficient of thermal expansion (CTE) of copper is much higher than that of silicon. The package materials with different CTEs will induce large stresses at interfaces. In order to overcome this problem, copper should be substituted by tungsten. However, tungsten cannot be directly plated from an aqueous electrolyte, it can be co-deposited with iron group metals. Alternatively, since the CTE of graphene is much closer to silicon than copper, we choose graphene sheets to substitute copper seed layer.Traditional process for TSV fabrication is a dry process that includes the following step: (1) formation of vias by reactive ion etching; (2) formation of a SiO2isolation layer; (3) deposition of a TiN barrier layer and a copper seed layer; (4) electrodeposition of copper inside the via. In our research, we reduce the procedure of TSV fabrication using a wet process to substitute barrier and seed layer with graphene, and electrodeposition with Ni-W alloy to make a copper-free TSV. In other words, a copper-free TSV with simplified process steps is fabricated, leading to a low fabrication cost. Moreover, a low-stress TSV filled with low CTE materials (Ni-W and rGO) is also fabricated to improve the thermo-mechanical fatigue of TSV, leading to better package reliability.

Numerical Analysis of the Correlation between the Cu+ Ion Concentration and the Current Density

Introduction 3D chip stacking realize high-density packaging and high-speed performance. High-aspect-ratio through-silicon via(TSV) allow short interconnects and reduced signal delays. This TSV interconnection will be applied to wide I/O memories of the next generation smart phone. Cu electrodeposition in high-aspect-ratio via is one of the key technologies for 3D packaging. Voids or seams formed in the via may causes serious problems in reliability. The formation of the Cu+ ion is a crucial intermediate and the Cu+ion intermediate is always produced during the electrodeposition process (eq.1 and 2). We already reported that 4 μm diameter via of aspect ratio of 7.5 is perfectly filled with the increasing Cu+ ion concentration inside the via[1,2]. Additionally, K. Kondo et al. have reported that a large amount of Cu+ ion within the confined area of the trench of the trench bottom electrodes and experimentally verified the relation between the Cu+ ion and acceleration[3]. In this study, we have calculated the Cu+ion concentration shifting at the trench bottom during electrodeposition by using COMSOL Multiphysics. Numerical Analysis The simulation model is shown Fig.1. We have assumed that the electrode surface is only trench bottom. And the reaction equations of Cu2+ ion and Cu+ ion at trench bottom are shown eq.3 and 4. The reaction kinetic parameters, k1, k-1, k2 and k-2 have been reported our previous study[2]. The reaction kinetic parameter from Cu2+ ion to Cu+ ion, k1 as 8.4×10-8 m/s, that from Cu+ ion to metallic Cu, k2 as 5.5×10-5 m/s, that from Cu+ ion to metal Cu2+, k-1 as 7.0×10-6 m/s, that from metallic Cu to Cu+ ion, k-2 as 1.6×10-8 m/s. Additionally, the diffusion equations in the electrolyte are shown eq.5 and 6. In this simulation model, the reverse current has been applied from 1 to 13 s, and the off-time has been applied from 0 to 1 s and 13 to20 s. Results and discussion We have calculated the Cu+ ion concentration shifting at the trench bottom with various trench widths. The calculation results are shown in Fig. 2. From Fig. 2, we have understood that the Cu+ ion concentration increase with the reverse current(1s to 13 s) and the off-time(13s to 20 s) with narrowing trench widths. Figure 3 shows the result of LSV measurements by using trench-shaped through mask electrode that reported in reference 3. Before measurements, the trench bottom electrode has been dissolved for 12 s with 10 mA/cm2 in order to produce Cu+ ion at the trench bottom. From Fig. 3, we have understood the current density increase with narrowing trench widths.Cu(I)Thiolate formation and acceleration effect will be discussed at the meeting.[1] T. Hayashi et al., J. Electrochem. Soc., 160(6) D256 (2013).[2] T. Hayashi et al., ECS 224thMeeting (2013).[3] K. Kondo et al., ECS Electrochem Lett., 3(4) D3 (2014).

Through-Silicon-Via(TSV) Filling by Electrochemical Deposition with Pulse-Reverse Current

TSV interconnection was widely investigated for next generation integrated-circuit(IC) which has significantly innovated function, excellent performance and high efficiency. Especially, TSV filling process by Cu electrochemical deposition occupied almost 40% of cost in the total TSV process. Therefore, a plenty effort has been put into decrease the processing time and prevent the formation of defects such as void or seam which could cause critical electrical and mechanical problems in the device. In the past, TSV filling studies were mainly focused on the function of chemical additives or bottom-up filling mechanism. In these kinds of researches, TSV filling process window was extremely limited because the applied current in the electrochemical process was a simple direct current or a constant voltage condition. Therefore, TSV filling by electrochemical deposition with pulse current was reported by our group for achieving the extensively wide process window. In this study, TSV filling by electrochemical deposition with pulse-reverse current was carried out for achieving even more extended process window.Electrochemical deposition experiments were carried out in the 1 M CuSO4 electrolyte with suppressor and accelerator. TSV (diameter: 6 μm, depth: 60 μm) coupon sample and Pt electrode was used as working and counter electrode, respectively. Pulse-reverse current was consisted with the peak current (ipeak) and the reverse current (irev) that applied during the on time (ton) and the reverse time (trev) period, respectively. (figure 1) During the on time and reverse time period, deposition and dissolution of Cu was occurred, respectively. The average current (iavg) could be calculated by equation in the figure 1. Peak current density and on time used in this study was fixed to 450 mA/cm2 and 2 μs, respectively. Vertically filled shapes of electrodeposited TSVs were observed by optical microscope (OM). Through achieved images, “bottom-up filling ratio” and “side wall growth ratio” was calculated for analyzing the TSV filling performance.Figure 2a shows the effect of reverse current density. The average current density and processing time was fixed to 2 mA/cm2 and 15 min, respectively. Bottom-up filling ratio was decreased with decreased reverse current. However side wall growth ratio was increased. These results were mainly caused by following reasons. Desorption of suppressor on the side wall during the reverse time was accelerated by increased reverse current. Even the ion depleted layer might be thicker due to decreased anodic current efficiency during the reverse time. Insufficiently relaxed ion depleted layer caused increasing the peak overpotential during the on time period. High overpotential caused accelerating the desorption rate of suppressor. Therefore, inhibition effect on the side wall was decreased, and thicker side wall was formed. Bottom-up filling ratio was naturally decreased because diffusing cupric ions from the top to the bottom of the via was preferentially consumed on the side wall.Figure 2b shows the effect of increased average current density in fixed reverse current density (irev = 5 mA/cm2). Both bottom-up filling ratio and side wall growth ratio was increased as average current density increased due to increased average current density. However, TSV filling mode was suddenly changed to conformal filling at the 5 mA/cm2. This result was mainly caused by following reason. Reverse time was decreased to increase the average current density in fixed reverse current condition. Decreased reverse time caused insufficient ion supplying to the ion depleted layer and ion depleted layer thickness was increased. Therefore, decreased bottom-up filling and increased side wall growth was occurred due to same reason as case of controlling the reverse current.

Full RLGC model extraction of Through Silicon Via (TSV) with charge distribution effects

The analytical model based on Poisson–Boltzmann equation in a cylindrical coordinate system is developed for simulating the electrical parameters of the three-dimensional Through Silicon Via (TSV) interconnection. Considering the effects of bias voltage, the accurate charge distribution and the high-frequency capacitance in the depletion layer of the semiconductor is obtained. Moreover, the resistance and inductance parameters of TSV are extracted by using the partial element equivalent circuit method. Finally, the full resistance–inductance–capacitance–conductance electrical model of TSV interconnection is presented first time with the semiconductor behaviour, and the transmission characteristics of signal-ground TSV structure are studied.

(Invited) Microwave-Based Metrology Platform Development: Application of Broad-Band RF Metrology to Integrated Circuit Reliability Analyses

Three dimensional stacked integrated circuits (3D-ICs), achieved using through-silicon vias (TSV), is an enabler for the continued miniaturization, increased performance and functional diversification of microelectronic devices. However, their introduction to the market has been hindered by many reliability challenges; in particular, stress related failures in this new technology are significantly worse than the traditional planar integrated circuits. For example, the large mismatch in the coefficient of thermal expansion (CTE) of the silicon matrix (~2.3 ppm/ºC) and the copper TSV (~17 ppm/ºC) interconnects, results in the buildup of stresses. This introduces a new reliability challenges such as the degradation of transistors and other front-end-of-line (FEOL) devices, in close proximity to the TSVs [2].By and large, stress is the root cause of most microelectronic devices reliability failures; it has been reported that 65% of all microelectronic device failures are thermo-mechanical related, mostly due to thermally induced stresses and strains stemming from the mismatch in the neighboring dissimilar materials [1]. The stress evolution leads to stress buildup, resulting in the generation of defects such as cracks, voids, delamination, plastic deformation, warpage and buckling. These damages could ultimately lead to open or short circuits in the microelectronic chip, resulting in their failure.Metrology for accurate understanding and quantification of the impact of stress evolution in 3D-ICs structures is key to addressing stress-related reliability challenges associated with the 3D-IC technology. In this presentation, we discuss our attempts to identify and characterize types of performance-limiting defects in three-dimensional (3-D) nanoelectronic devices, with special focus on 3-D interconnects, and relate the defects to the evolution of stress, where and why they form within the samples studied. In addition, we discuss non-destructive techniques for identifying such performance-limiting defects, without interrupting the responsible mechanistic phenomena [3]. References B. Wunderle, B. Michel et al, “Progress in Reliability Research in the Micro and Nano Region.” Microelectronics and Reliability, Vol. 46, pp. 1685-1694.A. Mercha et al, Comprehensive Analysis of the Impact of Single and Arrays of Through Silicon Vias induced Stress on High-k / Metal Gate CMOS Performances”, International Electron Devices Meeting (IEDM), Dec. 2010, San Francisco, CA, USA, pp. 2.2.1 -2.2.4.C. Okoro et al., “Accelerated Stress Test Assessment of Through-Silicon Via using RF Signals,” IEEE Transaction on Electron Devices. Vol. 60, No.6, 2013, pp 2015-2021