Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment

Abstract

The vertical interconnects between the components of a 3D system-on-chip (SoC) are realized by through-silicon vias (TSVs). These large global vias are a frequent performance bottleneck due to their high capacitive crosstalk. In order to reduce it, this work analyses the effect of temporal misalignment between the transitions on the signal nets of an interconnect structure and presents a technique to exploit it. The approach, based on a crosstalk-aware net-to-TSV assignment and hardware-efficient low-power codes, enables a dramatic improvement in the 3D interconnect performance. Circuit simulations show that the proposed technique reduces the delay and the noise of modern TSV interconnects by about 35%–50%, without noticeable cost. In combination with the classical bus invert coding, an additional decrease in the energy consumption by about 17% is obtained.