Abstract

A through-silicon via (TSV) is a conducting copper nail, which provides an electrical connection through a substrate, and is expected to be used extensively to provide high-speed interconnects between the top and bottom of an active die. However, some TSV structural defects such as pinholes and voids are difficult to capture as they commonly affect TSV performance parameters rather than TSV logical function. In order to electrically detect failures, it is necessary to study and analyze electrical characteristics of defects in advance. Testing TSV interconnects for manufacturing defects poses major challenges, and new design-for-test techniques are needed. Here, a novel nondestructive defect detection method using machine learning (ML) is proposed in order to detect void, short, and open defects in TSV-based 3-D ICs. A supervised ML approach is used to build a classification model from training S-parameter data sets containing the defected TSV and the normal TSV. The performance of the random forest classifier is tested for various amounts of void, short, and open defects in TSV-based 3-D-stacked ICs with satisfactory results.

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