Through Glass Via Research Articles

An optimized Ni[sbnd]P seed layer coating method for through glass via (TGV)

Through Glass vias (TGV) metallization can realize the interconnection of components between the circuit boards. Metallic seed layer is required in order to realize copper filling through via. Vias are created by hydrofluoric acid etching based on photosensitive glass. The glass modification only adopts physical roughening instead of chemical modification. The paper chose Nickel activation and NiP electroless plating. Nickel activation process were optimized so that seed layer completely covered the glass with high aspect ratio (10:1). Annealing treatment was studied for improving the contact adhesion. The NiP seed layer achieves electroplating filling function.

Development of 3-D Wafer Level Packaging for SAW Filters Using Thin Glass Capping Technology

The introduction of 5G mobile communication created the need to support a large number of radio frequency (RF) bands. This required high performance and reduced size for microacoustic filters. Based on these requirements, a new three-dimensional wafer-level packaging (3-D WLP) solution based on the predecessors’ developed technology was presented to resolve reliability issues for surface acoustic wave (SAW) filter packages with large cavities. In the 3-D WLP, vertical interconnects were realized using through glass vias (TGVs). To enable such a process scheme, thin glass caps with TGVs were formed through laser-induced chemical etching. Then, glass capping dies were bonded on the corresponding LiTaO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> (LT) device wafer to generate a cavity structure. Partial filling of the vias on the pad was used, and a metal trace was formed on the glass. Ball grid arrays (BGAs) were formed on top of the glass. Finally, an SAW filter WLP was fabricated. This glass capping packaging avoids the outgassing problem of conventional thin-film acoustic packaging at high temperatures, which would cause the contamination of the interdigital transducers (IDTs). In addition, a numerical study based on the 3-D finite element (FE) model has been conducted to analyze the reliability of the package. The built model was applied to perform parametric studies on the effects of package geometry, material properties, and the processing conditions on reliability. Based on the above studies, the optimized SAW filter WLP successfully passed the reliability test of pre-con level 3 and temperature cycling test (TCT, −40 °C ~ 125 °C).

Fabrication of Through-glass Vias (TGV) based 3D microstructures in glass substrate by a lithography-free process for MEMS applications

Fabrication of Through-glass Vias (TGV) based 3D microstructures in glass substrate by a lithography-free process is presented. Through-holes having an opening size of ∼ 300–500 µm and spiral-shaped embedded redistribution lines of ∼ 290 µm width and ∼ 50 µm depth were directly created in a 400 μm thick glass substrate by the electrochemical discharge machining. A 20 nm thick conformal seed layer was deposited by electroless nickel deposition, which can be a cost-effective alternative to vacuum-based physical vapor deposition techniques. The surface morphology of the electroless layer was characterized using an atomic force microscope and field emission scanning electron microscopy. Scotch-tape test showed a good adhesion of the seed layer with the glass substrate. Copper electrodeposition was performed to increase the thickness, after which thermal annealing was carried out to release the residual stress in the film. The adhesion of electrodeposited copper significantly improved after thermal annealing at 240 °C for 30 min. Electrodeposition is performed again to increase the thickness to the desired level. The current–voltage characterizations show good connectivity, and the average electrical resistance of a 3-turn square-shaped 3D microstructures is 2.41 Ω. Other spirals and square-shaped designs are also fabricated to prove the flexible capability of this ‘lithography-free’ technique.

In-situ temperature-dependent characterization of copper through glass via (TGV)

Glass has been proposed as a promising material for interposer because of its outstanding material properties. The development of through-glass via (TGV) technology is the most challenging process in the fabrication of glass interposers. This study investigates thermomechanical responses of TGVs induced by thermal loading. Optical profilometry was used to measure the protrusion of copper vias during thermal cycling. The TGV was heated from room temperature (RT) 23 °C to 400 °C and then cooled to RT. The height of an irreversible copper protrusion was recorded at different temperatures. In-plane deformation of the glass caused by thermal mismatch is investigated. Two-dimensional digital image correlation (2D DIC) was applied to measure the in-plane deformation of the glass near the copper via during thermal cycling. The in-plane displacement of the glass near copper vias reached its maximum around 250 °C, then started decreasing because of the copper protrusion and the significant creep of copper material at elevated temperatures. The effect of temperature ramp rate (4 °C/min, 15 °C/min, 30 °C/min, 50 °C/min) on the in-plane deformation of the glass was studied. The in-plane deformation of the glass can be reduced be applying slower ramp rate, because more significant creep occurs in the copper with slower ramp rate which alleviates the CTE mismatch-induced thermal stress at the copper-glass interface. Measurements were conducted to study the creep behavior of the copper via at different temperatures with one hour duration. Each of four TGV samples was heated to a peak temperature, 100 °C, 200 °C, 300 °C, and 400 °C, respectively, and the temperatures were held for 1 h. The glass in-plane displacements were measured by a 2D DIC. Numerical simulations were performed to provide an insight into the thermomechanical behavior of the copper vias and the glass during thermal cycling. The equivalent creep strain of the copper and the maximum principal stress of the glass are presented based on the simulation results.

Glass Package for Radar MMICs Above 150 GHz

This work presents a novel sensor packaging and a novel transition concept for radar applications above 150 GHz based on glass material. By using laser induced deep etching (LIDE) technology, glass vias and cavities are fabricated without degrading the mechanical stability of glass, as micro-cracks are completely avoided. Especially at high millimeter wave (mm-wave) frequencies, precise structuring on low dielectric loss materials and a high integration density are essential for low loss transitions. In this paper, an ultra compact FMCW radar monolithic microwave integrated circuit (MMIC) at 160 GHz is used to demonstrate this packaging technology. In addition, the high frequency signal is guided by a low loss transition to a deposed antenna via a dielectric waveguide (DWG) providing the antenna front end with mechanical flexibility. Thus, using plated through glass vias (TGVs) and a circulating solder ring, the package is hermetically sealed. The optical transparent glass package has a size of only <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${5.8}\,\rm {mm}\times {4.4}\,\rm {mm}\times {0.9}\,\rm {mm}$</tex-math></inline-formula> . A minimum measured insertion loss of 2.85 dB at 162 GHz from chip to DWG is achieved. The complete radar system with a range resolution of 12 mm is demonstrated via radar measurement.

A T-Model With Parameter Extraction Method for Modeling 3-D Spiral Inductor

A new frequency-independent modified T-equivalent circuit for 3-D spiral inductor is proposed in this letter. Closed-form analytical expressions are proposed account for configuration and physics-based effect. Compared with double-π model, it uses less number of elements to capture the self-resonant frequency (SRF) information. Compared with the existing T-model, it can accurately reflect the characteristics that effect series resistance (ESR) increases of frequency at first and decreases at higher frequency. Verification with measurement data based on through glass vias (TGVs) process up to 20 GHz demonstrates excellent performance prediction.

Fabrication of 32 × 32 2D Capacitive Micromachined Ultrasonic Transducer (CMUT) Arrays on a Borosilicate Glass Substrate With Silicon-Through-Wafer Interconnects Using Sacrificial Release Process

Close integration of transducer arrays with supporting electronic circuits is essential in achieving efficient and compact ultrasound systems. An integral part of hybrid integration of 2D CMUT array to CMOS electronics is the introduction of through-glass-via (TGV) interconnects in glass substrates as an integral part of the 2D CMUT array fabrication. Micro-cracks around via locations, via discontinuity, and poor coplanarity between the vias and glass substrate are some of the challenges with laser-drilled, paste-filled copper-through-glass-via (Cu-TGV) interconnects. This study provides a detailed fabrication process for making <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$32\times 32$ </tex-math></inline-formula> -element 2D CMUT arrays on a composite glass substrate incorporating silicon-through-glass vias (Si-TGV) as interconnects using sacrificial release approach. On one column of a fabricated 2D CMUT array, we measured a mean resonant frequency of 5.6 MHz in air and an average device capacitance of 1.5 pF. With the introduction of a buried top electrode in the device structure, we achieved a collapse voltage of 93 V, which is considerably lower than the collapse voltage measured in our previously demonstrated 2D CMUT arrays with top electrode on top of the nitride plate. The fabricated array is flip-chip bonded on a custom-designed driving integrated circuit to demonstrate the complete system operation. We measured a peak-to-peak pressure of 1.82 MPa at 3.4 MHz, and 5 mm from the array surface in a 0.33 mm focal spot size. [2021-0101]

Design and fabrication of through-glass via (TGV) based 3D spiral inductors in fused silica substrate

Design and fabrication of through-glass via (TGV) based 3D spiral inductors in fused silica substrate

Measurement and Analysis of Through Glass Via Noise Coupling and Shielding Structures in a Glass Interposer

In this article, we first measured through glass via (TGV) noise coupling and the effectiveness of shielding structures in a glass interposer. To analyze the noise coupling between signal TGVs, an open-ended structure is adopted. Glass interposer test vehicles were fabricated to verify the noise coupling between signal TGVs. With these test vehicles, noise transfer functions between signal TGVs were measured. Based on these measurement results and the equivalent circuit model, the noise coupling between signal TGVs was analyzed. To suppress this TGV noise coupling, shielding structures for the TGV noise coupling were proposed and verified. The proposed shielding structures include the variation of signal TGV pitches and the number of grounded shield TGVs, ground pads, and guard rings, respectively. The effectiveness of the proposed shielding structures was verified up to 20 GHz in frequency-domain measurements. Using the proposed shielding structures, the noise transfer function decreased by 9.4 dB at 5 GHz. Also, the effectiveness of the proposed guard ring structure was verified by a time-domain coupling noise simulation with clock signals at frequencies of 1 GHz. The proposed guard ring successfully suppressed the clock noise coupling between signal TGVs by 60.5% and 69.2% when a signal TGV pitchis 300 and 900 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu {\text{m}}$</tex-math></inline-formula> , respectively.

Robust Pressure Sensor in SOI Technology with Butterfly Wiring for Airfoil Integration.

Current research in the field of aviation considers actively controlled high-lift structures for future civil airplanes. Therefore, pressure data must be acquired from the airfoil surface without influencing the flow due to sensor application. For experiments in the wind and water tunnel, as well as for the actual application, the requirements for the quality of the airfoil surface are demanding. Consequently, a new class of sensors is required, which can be flush-integrated into the airfoil surface, may be used under wet conditions—even under water—and should withstand the harsh environment of a high-lift scenario. A new miniature silicon on insulator (SOI)-based MEMS pressure sensor, which allows integration into airfoils in a flip-chip configuration, is presented. An internal, highly doped silicon wiring with “butterfly” geometry combined with through glass via (TGV) technology enables a watertight and application-suitable chip-scale-package (CSP). The chips were produced by reliable batch microfabrication including femtosecond laser processes at the wafer-level. Sensor characterization demonstrates a high resolution of 38 mVV−1 bar−1. The stepless ultra-smooth and electrically passivated sensor surface can be coated with thin surface protection layers to further enhance robustness against harsh environments. Accordingly, protective coatings of amorphous hydrogenated silicon nitride (a-SiN:H) and amorphous hydrogenated silicon carbide (a-SiC:H) were investigated in experiments simulating environments with high-velocity impacting particles. Topographic damage quantification demonstrates the superior robustness of a-SiC:H coatings and validates their applicability to future sensors.

Elimination of Thermo-Mechanically Driven Circumferential Crack Formation in Copper Through-Glass via Substrate

This work aims at understanding and eliminating thermo-mechanically induced circumferential cracks that form during cooling for a 400 °C annealed copper (Cu) through-glass via (TGV) with a mean outer diameter of 47.5 μm, made in Corning HPFS fused silica glass. An exponential dependence was found between Cu metallization thickness and the likelihood for the formation of circumferential cracks. For the conditions used in this study, no cracks were formed in the HPFS fused silica substrate for Cu metallization thicknesses <; 12 μm, however, for thicknesses ≥ 12 μm, circumferential crack formation exponentially increased. From finite element analysis (FEA) studies, the corresponding threshold stresses for the initiation of circumferential stresses at 12 μm was predicted to be 140 MPa. Therefore, for 400 °C annealed Cu TGV with a mean outer diameter of 47.5 μm, made in HPFS fused silica substrate, circumferential stresses can be eliminated when Cu metallization thickness of less than 12 μm is used.

Engineered Ceria Slurries for Electronic Glass Substrate CMP Application

Glass substrates have gradually gained more attention as the media platters in hard disk drives (HDD) used in laptops, data centers, and cloud storage due to its advantageous properties. Particularly, advanced technologies like Heat Assisted Magnetic Recording (HAMR) in HDD and Through-Glass-Via (TGV) in 3D packaging applications all require the use of glass substrates with precisely controlled surface properties. Glass substrate’s advantages include lower weight, improved flatness, less flutter at high RPM’s and lower thermal expansion as compared to aluminum / NiP substrates. This lower expansion when exposed to heat makes it ideal for HAMR technology, which will be the key to creating hard disk drives with growing storage capacity. Chemical mechanical polishing (CMP) is a method to eliminate surface defects induced by grinding & lapping to meet final requirements of HAMR or TGV for glass substrates with surface finishes down to a few angstrom level or less. Key performance targets include removal rate, surface roughness, TTV, FSW, ceria residue / particle content (cleanability) on glass disks as well as recyclability. In this study, slurries for CMP are investigated utilizing engineered ultra-pure ceria particles which are known to have high material removal rate (MRR) on glass substrates. Various particle sizes, morphology, and chemical additives were evaluated. Results of systematic CMP tests including MRR, surface roughness, recyclability, and most importantly, ease of ceria residue removal from the glass substrate will be reported. Morphology of ceria particles was found to play a critical role in MRR. An optimized combination of ceria morphology and additive chemistries enables high MRR together with improved Ceria residue / cleanability performance. Figure 1

Effect of ZnO on dielectric properties of Li-Al-Si photoetchable glasses as an interposer

In current three-dimensional (3D) radio frequency (RF) package field, the silicon interposer can’t entirely meet the needs of the package because of its non-negligible dielectric loss. Similarly, the application of through Glass vias (TGV) has restriction for the same reason. Therefore, this paper focuses on reducing dielectric loss of photoetchable glass (PEG), as well as the performance of TGV technology of PEG for packaging. The PEG was reduced in the dielectric loss by the addition of ZnO. The reduction in dielectric loss is due to changes in structure. The structure of PEG was analyzed through the XRD and the Raman spectroscopy. The dielectric performance was verified by the Impedance Analyzer. The result indicated dielectric loss obviously decreased to 0.0035 by ZnO doped and the reason primarily attributed to the decrease number of the Non-Oxygen-Bridge in the glass network and the structure is more stable. Through thermal processes and etching, the average diameter obtained around 75μm by TGV, and the aperture ratio of up to 25: 1, TGV density can reach 10000 / cm2.

Understanding and eliminating thermo-mechanically induced radial cracks in fully metallized through-glass via (TGV) substrates

This work aims to understand and eliminate the formation of thermo-mechanically induced radial cracks in copper (Cu) metallized through-glass via (TGV) substrates made of Corning® high purity fused silica (HPFS® fused silica), after subjection to 420 °C annealing treatment. Radial cracks were found to be formed in Cu TGV substrate during the heating step of annealing treatment process, caused by high stress buildup resulting from the large mismatch in the coefficient of thermal expansion (CTE) between the HPFS® fused silica substrate and the Cu metallization. From analytical studies, high tensile circumferential stresses were found to be the main stress component that is responsible for the formation of radial cracks during heating. From experimental studies, it was found that radial crack formation was exponentially dependent on the applied heating rate, and that faster heating rate increased the probability for their formation. However, a crack-free metallized TGV substrate was achieved when heating rates ≤6.5 °C/min was applied, thus, eliminating radial crack formation. Radial crack elimination was attributed to the significant activation of stress relaxation mechanisms in the Cu. This was confirmed by the measurement of an inverse dependence of Cu protrusion with the applied heating rate. Additionally, the Cu protrusion data confirms that the leading stress relaxation mechanisms in the Cu TGV were grain boundary sliding (GBS), plastic deformation and Coble diffusional creep.

Time and Temperature Dependence of Copper Protrusion in Metallized Through-Glass Vias (TGVs) Fabricated in Fused Silica Substrate

In this work the influence of annealing dwell time and temperature, as well as post-annealing thermal processing treatment on copper (Cu) protrusion in Cu through-glass vias (TGVs) were studied. The Cu TGVs were made in Corning HPFS Fused Silica substrate, with a diameter and depth of 50 μm and 300 μm, respectively. For a constant annealing temperature of 400 °C, the results show a dependence of Cu protrusion with annealing dwell time, which saturates at about 240 min. Additional post-annealing thermal processing treatment, done at 400 °C (60 min dwell time) revealed that when an annealing dwell time ≥ 120 min is used no difference in the amount of Cu protrusion was found between the annealing step and the post-annealing thermal processing step. This indicates that downstream Cu protrusion can be eliminated when an annealing dwell time ≥ 120 min is used. On the other hand, from the temperature - dependent study of the annealing treatment, it was found that downstream Cu protrusion occurrence can be eliminated by performing annealing treatment at 450 °C (60 min dwell time), followed by post-annealing thermal processing treatment of 400 °C (60 min dwell time). Therefore, downstream Cu protrusion from a thermal processing treatment of 400 °C with 60 min dwell time can be eliminated either by using a longer annealing dwell time (120 min) at 400 °C or by increasing the annealing temperature to 450 °C, with a shorter dwell time of 60 min.

The effects of polyvinylpyrrolidone molecular weight on defect-free filling of through-glass vias (TGVs)

Through-glass vias (TGVs) have been extensively researched due to the unique properties of glass, including low dielectric constant, high transparency, high mechanical, thermal and chemical resistance, and low cost. The TGVs are typically filled with Cu by electrodeposition to make electrical connections in high-performance electronics with 3D integration. The Cu electrodeposition process employed to fill the through-holes is similar to the one used for printed circuit boards (PCBs), and defect-free Cu can be achieved with a butterfly filling mechanism. This study introduces the defect-free Cu filling of TGVs using polyvinylpyrrolidone (PVP) as a leveler. The effects of PVP molecular weight on the formation of suppression layers on the Cu surface was examined by electrochemical analyses. It was found that the smaller PVP (10,000g/mol) was beneficial, forming a more compact suppression layer. In contrast, the layer of larger PVPs (360,000g/mol) contained a large number of defects where the accelerator could adsorb, resulting in conformal electrodeposition. As a result, the PVP with a molecular weight of 10,000g/mol led to defect-free butterfly filling at TGVs with increasing the filling performance by 20% compared to the larger PVP.

The effect of materials and design on the reliability of through-glass vias for 2.5 D integrated circuits: a numerical study

PurposeThis study aims to investigate the factors responsible for substrate cracking reliability problem in through-glass vias (TGVs), which are critical components for glass-based 2.5 D integration.Design/methodology/approachNumerical models were used to examine the driving force for substrate cracking in glass interposers due to stress coupling during heating. An analytical solution was used to demonstrate how the energy release rate (ERR) for the glass substrate cracking is affected by the via design and the mismatch in thermal strain. Then, the numerical models were implemented to investigate the design factors effects, such as the pitch distance, via diameter, via pattern, via design, effect from a stress buffer layer and the interposer materials selection on the susceptibility to substrate cracking.FindingsERR for substrate cracking was found to be directly proportional to the via diameter and the thermal mismatch strain. When a via pattern is implemented for high-density integration, a coupling in the stress fields was identified. This coupling effect was found to depend on the pitch distance, the position of the vias, and the via arrangement, suggesting a via pattern-dependent reliability behavior for glass interposers. Changing the design of the via to an annular shape or a substrate-cored via was found to be a promising approach to reduce the susceptibility to substrate cracking compared to a fully filled solid via. Also, the use of a stress buffer layer, an encouraging design prospect presented for the first time for TGVs in this study, was found to significantly reduce cracking. Finally, alternative via and substrate materials showed lower tendency for substrate cracking, indicating that the reliability of glass interposers can be further enhanced with the implementation of such new materials.Originality/valueThis study signifies the first attempt to comprehensively evaluate the susceptibility to crack formation in glass interposers during heating. Therefore, this study provides new perspectives on how to achieve a significant potential reliability improvement for TGVs.

Influence of exposure energy and heat treatment conditions on through-glass via metallization of photoetchable glass interposers

Photoetchable glasses (PEGs) have been widely used in three-dimensional integrated circuits as interposers. However, the high costs associated with laser through-hole technology have limited their utilization in high-frequency circuitry and packaging. Ultraviolet lithography may reduce the cost and improve through-hole properties allowing PEGs to become a preferred practice and lend them to wider usage. Herein, we investigate the viability of PEGs by systematically studying the structural, compositional, and morphological properties of their through-hole composite structures as a function of several key process parameters including exposure energy and annealing conditions. Results indicate that both exposure energy and annealing temperature and duration have compensating effects. Optimized through-glass vias (TGVs) were determined to result from an annealing temperature of 560 °C, an annealing time of 60 min, and an exposure energy of 6 J/cm2. Metallization of through-holes was carried out using magnetron sputtering of an adhesion layer of Ti followed by a Cu layer. The morphology and composition of through-hole metallization, analyzed by electron microscopy and energy dispersive X-ray spectroscopy, revealed surfaces to have sharp, well-defined edges with smooth surfaces. The proposed PEG interposer processing methodologies described here offer renewed optimism for the efficient fabrication of channels and through-vias for microfluidic and integrated circuits and other three-dimensional electronic and hybrid systems.

Thin Glass Handling Solutions for Microelectronics Packaging

Abstract Glass substrates with fine-pitch through-glass via (TGV) technology gives an attractive approach to wafer level packaging and systems integration. Glass can be made in very thin sheets (&amp;lt;100 um thick) which aids in integration and eliminates the need for back-grinding operations. Electrical and physical properties of glass have many attractive attributes such as low RF loss, the ability to adjust thermal expansion properties, and low roughness with excellent flatness to achieve fine L/S. Furthermore, glass can be fabricated in panel format to reduce manufacturing costs. The biggest challenge to adopting glass as a packaging substrate has been the existence of gaps in the supply chain, caused primarily by the difficulty in handling large, thin glass substrates using standard automation and processing equipment. This paper presents a temporary bonding technology that allows the thin glass substrates to be processed in a semiconductor fab environment without the need to modify existing equipment.

Defect-free metallization of through-glass vias with engineered geometry in additive-free electrolyte

Defect-free metallization of through-glass vias (TGVs) with copper using an additive-free electrolyte is presented in this communication. Engineered vias with an X-shape in the middle were electroplated in the kinetic-limited regime (Thiele modulus, μ ≤ 1) to achieve pinching of the vias at the waist, after which continued conformal plating ensured void-free filling. Thiele modulus analysis and an 1D steady-state model predicted that the deposition front moves uniformly within the via when plating is carried out in the kinetic-limited regime. It was hypothesized that engineering the via geometry to an X-shape could enable pinching in the middle. However, neither of the two conditions are enough on their own to achieve defect-free filling. Combining these two allows conformal movement of the plating front and pinching in the middle, which results in complete filling of the via. While additive-based bath is required and will continue to be used to optimize between plating speed, low stress and roughness of plated copper, the objective of this article is to demonstrate the advantage of engineered vias in which even an additive-free bath could provide defect-free metallization. At very low current densities, an anomalous increase in thickness in the middle compared to the top of the via was observed. This cannot be explained by a simple 1D model and is an interesting next step in understanding additive-free electroplating.