Threshold Voltage Variation Research Articles

Threshold Voltage based Dual Memristor Crossbar PUF

IoT security plays a crucial role where smart devices are interconnected and one of these can give an intrusion access to the network if they are not secured. Physical unclonable function (PUF) comes in handy as an emerging lightweight hardware security primitive for key management and device authentication. In this research work, we propose a new architecture of PUF hardware based on memristor threshold voltage variation. Memristor manufacturing variations are exploited for the threshold voltage variation which makes the device unique. The selection from the proposed crossbars forms two connected memristors. The selections connect the formed voltage divider network to the input and ground. The output is probed at the middle node, which is the selected rows of the two crossbars. Voltage (challenge) is applied at selected pair of memristors through the corresponding columns and rows, and output (response) is taken from the selected rows. We believe this work will set a new direction for the researchers to explore manufacturing errors for PUF applications.

Design of a 0.4 V, 8.43 ENOB, 5.29 nW, 2 kS/s SAR ADC for Implantable Devices

This paper presents a 9-bit differential, minimum-powered, successive approximation register (SAR) ADC intended for implantable devices or sensors. Such applications demand nanowatt-range power consumption, which is achieved by designing the SAR ADC with a proposed bootstrap switch, bespoke split-capacitive DAC, customized comparator and a modified dynamic bit-slice unit for SAR logic. The linearity of the ADC is improved by introducing a bootstrap switch with a low clock feedthrough and threshold voltage variations along with the disseminated attenuation capacitor in the split-capacitive DAC. The dynamic comparator is customized to be simple in terms of the number of transistors to gain the advantage of low power and is also designed to have a low dynamic offset voltage. The stacking concept is embedded in the bit-slice unit of SAR logic to achieve reduced leakage power. This paper is concerned with how to contribute to low power consumption in all the aspects possible related to the implementation of the SAR ADC. With a 0.4 V supply and at 2 kS/s, the proposed ADC achieves an SNDR of 52.52 dB and a power consumption of 5.29 nW, resulting in a figure of merit (FOM) of 7.66 fJ/conversion-step.

Insights into the impact of random dopant fluctuation on ferroelectric germanium source vertical TFET

This paper investigates the effect of random dopant fluctuation (RDF) on the performance of ferroelectric Germanium source vertical tunnel field effect transistor (FE GeS-vTFET) using 3-D device simulation. The variation in the on-state current (σION), off-state leakage current (σIOFF), current ratio σ(ION/IOFF), subthreshold swing (σSS), threshold voltage (σVTH), total gate capacitance (σCgg), transconductance (σgm) and cut-off frequency (σfT) for different source doping concentration and source thickness due to the effect of RDF are evaluated. The findings indicate an increasing tendency in RDF with higher doping concentration in the source region. The variation in the on-current is from 0.2173 mA to 0.2337 mA (∼1.075 times higher), and σIOFF varies from 4.939 fA to 16.545 fA (∼3.349 times higher) from 1 × 1020 /cm3 to 3 × 1020 /cm3 doping concentration, respectively for Germanium source thickness of 12 nm. RDF within the source region mainly contributes to the threshold voltage variation of about 92 % in all regions. The randomized dopant-induced σVTH for the FE GeS-vTFET compared with other field effect transistors of the same technology node showed a substantial reduction in σVTH, signifying that the device is more immune to the effects of RDF. Furthermore, the effect of temperature on the switching properties of the FE GeS-vTFET has been studied.

Coaxial boron nitride nanotubes as interfacial dielectric layers to lower interface trap density in carbon nanotube transistors

A semiconductor/dielectric interface is one of the dominant factors in device characteristics, and a variety of oxides with high dielectric constants and low interface trap densities have been used in carbon nanotube transistors. Given the crystal structure of nanotubes with no dangling bonds, there remains room to investigate unconventional dielectric materials. Here, we fabricate carbon nanotube transistors with boron nitride nanotubes as interfacial layers between channels and gate dielectrics, where a single semiconducting nanotube is used to focus on switching behaviors at the subthreshold regime. The subthreshold swing of 68 mV·dec−1 is obtained despite a 100-nm-thick SiO2 dielectric, corresponding to the effective interface trap density of 5.2 × 1011 cm−2·eV−1, one order of magnitude lower than those of carbon nanotube devices without boron nitride passivation. The interfacial layers also result in the mild suppression of threshold voltage variation and hysteresis. We achieve Ohmic contacts through the selective etching of boron nitride nanotubes with XeF2 gas, overcoming the trade-off imposed by wrapping the inner nanotubes. Negligible impacts of fluorinating carbon nanotubes on device performances are also confirmed as long as the etching is applied exclusively at source/drain regions. Our results represent an important step toward nanoelectronics that exploit the advantage of one-dimensional van der Waals heterostructures.

Negative capacitance field-effect transistors based on ferroelectric AlScN and 2D MoS2

Al0.68Sc0.32N (AlScN) has gained attention for its outstanding ferroelectric properties, including a high coercive field and high remnant polarization. Although AlScN-based ferroelectric field-effect transistors (FETs) for memory applications have been demonstrated, a device for logic applications with minimal hysteresis has not been reported. This study reports on the transport characteristics of a MoS2 negative capacitance FET (NCFET) based on an AlScN ferroelectric material. We experimentally demonstrate the effect of a dielectric layer in the gate stack on the memory window and subthreshold swing (SS) of the NCFET. We show that the hysteresis behavior of transfer characteristics in the NCFET can be minimized with the inclusion of a non-ferroelectric dielectric layer, which fulfills the capacitance-matching condition. Remarkably, we also observe the NC effect in MoS2/AlScN NCFETs arrays based on large-area monolayer MoS2 synthesized by chemical vapor deposition, showing the SS values smaller than its thermionic limit (∼36 to 60 mV/dec) and minimal variation in threshold voltages (<20 mV).

Modelling SiC MOSFET module threshold voltage (VTH) and impact of parallel device ΔVTH on short circuit robustness

In SiC modules, where several power MOSFETs are connected in parallel for high current conduction capability, the issue of threshold voltage (VTH) variation between individual devices can become problematic. In instances where the standard deviation of device VTH is minimized by appropriate VTH pre-screening, non-uniform VTH shift under bias-temperature-instability can lead to increased VTH dispersion and potentially poor current sharing. Although non-destructive for normal operation, VTH dispersion in surge events like short circuits can cause premature module failure. In this paper, experimental investigations backed by theoretical models have been developed to explain the relationship between device VTH dispersion and module VTH shift. This is done for Si and SiC MOSFETs. Five Si/SiC MOSFETs are paralleled in a custom printed-circuit-board allowing individual VTH and module VTH measurements. It is shown that the module VTH is typically between the smallest VTH and the mean VTH, depending on the VTH standard deviation. Using empirical models for MOSFETs in weak inversion derived from the measured subthreshold gate transfer characteristics, the model can estimate module VTH from a dispersion of individual MOSFET VTH. It can also predict the impact of non-uniform VTH shift between constituent devices on the overall module VTH. Finally, the impact of VTH mismatch on current sharing during short circuits in parallel connected SiC MOSFETs is presented. The results show that VTH mismatch in parallel connected SiC MOSFETs reduces the short circuit withstand time from 5 μs to 4.5 μs compared to VTH matched SiC MOSFETs.

Trade-off between gate leakage current and threshold voltage stability in power HEMTs during ON-state and OFF-state stress

We present a detailed investigation of the impact of electron gate leakage on the threshold voltage stability of normally-off GaN HEMTs with p-GaN gate. The analysis is based on combined DC, pulsed and transient measurements, carried out on two test wafers with different gate processes, resulting in different levels of gate leakage current. The key results demonstrate: (a) the existence of four different charge-trapping processes, whose interplay determines the sign and amplitude of the threshold voltage variation; (b) a reasonable increase in gate leakage is beneficial for eliminating the negative threshold voltage instability under positive gate bias, and for substantially reducing the positive threshold shift under off-state stress. Furthermore, (c) we present a proper characterization methodology for device understanding.

Impact of total ionizing dose on the alpha-soft error rate in FDSOI 28 nm SRAMs

Synergy effect of total ionizing dose (TID) on alpha-soft error rate (α-SER) in FDSOI 28 nm SRAM has been experimentally characterized using a dedicated setup combining alpha-particle irradiation (241Am solid source) in vacuum chamber and 10 keV X-ray irradiation. Measurements have been performed on a 3 Mbit single-port SRAM cut powered at 1 V. Irradiations up to 125 krad(Si) have been achieved and their impact on the α-SER has been characterized from the cumulated number of bitflips as a function of the exposition time to the alpha-source. Modelling and simulation have been used to link transistor threshold voltage variations to SRAM cell stability in terms of static noise margin (SNM), critical charge (Qcrit) and finally estimated SER, in good agreement with experimental results.

An Active-Matrix Organic Light-Emitting Diode Pixel Circuit Featuring Mobility Compensation for Portable Applications.

A 6T1C pixel circuit based on low-temperature polycrystalline oxide (LTPO) technology for portable active-matrix organic light-emitting diode (AMOLED) display applications is proposed in this paper. For superior high-end portable applications including 4K high resolution and high PPI (pixels per inch), the proposed pixel circuit employs a single storage capacitor and signal sharing switch-control design and provides low-voltage driving and immunity to the IR-drop issue and OLED degradation. Furthermore, the threshold voltage and mobility-compensating capabilities are improved by both compensation mechanisms, which are based on a negative feedback system, and mobility-related compensation parameters. Simulation results reveal that threshold voltage variations of ±0.33 V in the driving thin-film transistors can be well sensed and compensated while the maximum OLED current shift is 4.25%. The maximum variation in OLED currents within all gray levels is only 1.05% with mobility variations of ±30%. As a result, the proposed 6T1C pixel circuit is a good candidate for portable AMOLED display usage.

Composite stability and electro-optical properties of carbon nanotubes/5CB-based nematic hybrid liquid crystals

ABSTRACT This study examined the impact of different concentrations of carbon nanotubes (CNTs) on five nematic hybrid liquid crystals (LCs) based on 5CB. Electro-optical properties of the composite were tested, and the interaction between CNTs and LCs was theoretically analysed by first principles. Experimental results showed the effect of CNTs on electro-optical properties of hybrid LCs depended on the groups contained in monomer LCs. LCs with polar groups at the end increased the dielectric anisotropy of the composite, while the impact of CNTs on hybrid LCs containing non-polar terminal monomers was the opposite. The same variation was reflected in splay elastic constants and clearing points. Meanwhile, dielectric anisotropy, splay elastic constant, and rotational viscosity coefficients all changed with CNTs doping concentrations, reflecting the order of binding stability between representative groups and CNTs, and the variation of threshold voltage and response time reflected the order of binding stability between LC molecules and CNTs, consistent with theoretical calculations. Conductivity tests showed the additive of CNTs increased the conductivity of the composite and revealed the impact of CNTs on threshold voltage. Dielectric tests showed the incorporation of CNTs increased dielectric real and imaginary parts in low-frequency regions and increased relaxation frequency in high-frequency regions.

Single-Power-Supply Six-Transistor CMOS SRAM Enabling Low-Voltage Writing, Low-Voltage Reading, and Low Standby Power Consumption

We developed a self-controllable voltage level (SVL) circuit and applied this circuit to a single-power-supply, six-transistor complementary metal-oxide-semiconductor static random-access memory (SRAM) to not only improve both write and read performances but also to achieve low standby power and data retention (holding) capability. The SVL circuit comprises only three MOSFETs (i.e., pull-up, pull-down and bypass MOSFETs). The SVL circuit is able to adaptively generate both optimal memory cell voltages and word line voltages depending on which mode of operation (i.e., write, read or hold operation) was used. The write margin (VWM) and read margin (VRM) of the developed (dvlp) SRAM at a supply voltage (VDD) of 1 V were 0.470 and 0.1923 V, respectively. These values were 1.309 and 2.093 times VWM and VRM of the conventional (conv) SRAM, respectively.At a large threshold voltage (Vt) variability (=+6σ), the minimum power supply voltage (VMin) for the write operation of the conv SRAM was 0.37 V, whereas it decreased to 0.22 V for the dvlp SRAM. VMin for the read operation of the conv SRAM was 1.05 V when the Vt variability (= -6σ) was large, but the dvlp SRAM lowered it to 0.41 V. These results show that the SVL circuit expands the operating voltage range for both write and read operations to lower voltages. The dvlp SRAM reduces the standby power consumption (PST) while retaining data. The measured PST of the 2k-bit, 90-nm dvlp SRAM was only 0.957 μW at VDD = 1.0 V, which was 9.46% of PST of the conv SRAM (10.12 μW). The Si area overhead of the SVL circuits was only 1.383% of the dvlp SRAM.

Control of subthreshold swing using an in situ PEALD nano-laminated IGZO/Al2O3 multi-channel structured TFT

This study presents the development of multi-channel thin-film transistors (TFTs) using plasma-enhanced atomic layer deposition (PEALD) to stack layers of IGZO/Al2O3, with the number of stacking layers ranging from 1 to 10 (1S, 3S, 5S and 10S). To optimize the performance of the AM-LED display, the subthreshold swing (S·S) and mobility of each type of transistor, such as switching and driving transistors, were customized to meet specific requirements. The results show that as the number of stacking layers increased, the field-effect mobility (µ FE) improved by 323% from 1.34 to 4.33 cm2/Vs, while S·S improved by 0.14 V/dec from 0.31 to 0.45 V/dec, with no variation in threshold voltage (V th) and reliability. The study attributes the improvement in µ FE and S·S to the formation of multiple electron transport paths as confirmed by a TCAD simulation showing an increase in current density. Overall, this study demonstrates the potential of PEALD in creating multi-channel TFTs with improved performance by customizing oxide semiconductor properties. This research may have important implications in the development of advanced electronic devices that rely on thin-film transistors, as it provides a new approach in enhancing the performance of these devices.

FinFET 6T-SRAM All-Digital Compute-in-Memory for Artificial Intelligence Applications: An Overview and Analysis.

Artificial intelligence (AI) has revolutionized present-day life through automation and independent decision-making capabilities. For AI hardware implementations, the 6T-SRAM cell is a suitable candidate due to its performance edge over its counterparts. However, modern AI hardware such as neural networks (NNs) access off-chip data quite often, degrading the overall system performance. Compute-in-memory (CIM) reduces off-chip data access transactions. One CIM approach is based on the mixed-signal domain, but it suffers from limited bit precision and signal margin issues. An alternate emerging approach uses the all-digital signal domain that provides better signal margins and bit precision; however, it will be at the expense of hardware overhead. We have analyzed digital signal domain CIM silicon-verified 6T-SRAM CIM solutions, after classifying them as SRAM-based accelerators, i.e., near-memory computing (NMC), and custom SRAM-based CIM, i.e., in-memory-computing (IMC). We have focused on multiply and accumulate (MAC) as the most frequent operation in convolution neural networks (CNNs) and compared state-of-the-art implementations. Neural networks with low weight precision, i.e., <12b, show lower accuracy but higher power efficiency. An input precision of 8b achieves implementation requirements. The maximum performance reported is 7.49 TOPS at 330 MHz, while custom SRAM-based performance has shown a maximum of 5.6 GOPS at 100 MHz. The second part of this article analyzes the FinFET 6T-SRAM as one of the critical components in determining overall performance of an AI computing system. We have investigated the FinFET 6T-SRAM cell performance and limitations as dictated by the FinFET technology-specific parameters, such as sizing, threshold voltage (Vth), supply voltage (VDD), and process and environmental variations. The HD FinFET 6T-SRAM cell shows 32% lower read access time and 1.09 times better leakage power as compared with the HC cell configuration. The minimum achievable supply voltage is 600 mV without utilization of any read- or write-assist scheme for all cell configurations, while temperature variations show noise margin deviation of up to 22% of the nominal values.

Path-Based Delay Variation Models for Parallel-Prefix Adders

State-of-the-art static timing analysis algorithms can evaluate worst-case delay in statistical terms. In this paper, a modeling framework is introduced for the evaluation of the maximum-delay Cumulative Density Function (CDF) of an ensemble of parallel-prefix adder topologies. For moderate variations and close-to-nominal supply voltages, the maximum delay of parallel-prefix adders is practically determined by the maximum of a set of near-critical-delay paths around the nominal maximum-delay path. These paths end to the most significant and neighboring bit positions. Matrix-based path delay formulations are derived for the particular set of paths. The introduced matrix formulations are exploited to assess the maximum-delay CDF by means of a multivariate Gaussian CDF. To validate the accuracy of the introduced models, a quantitative comparison of the proposed probabilistic delay models against Spice-level Monte-Carlo simulations is offered for certain parallel-prefix adders. Threshold-voltage variations summarize several process-dependent variation-inducing mechanisms and are modeled as Gaussian variations, introduced to BSIM-4 transistor models for a 16-nm technology node. For the nominal voltage case and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$10\%$</tex-math></inline-formula> threshold-voltage variations, the introduced models estimate the 0.95 timing yield point with a mean absolute error below <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$1\%$</tex-math></inline-formula> compared to Spice-level simulations for the 16 bit-length case. Furthermore, an extension of the proposed approach to account for multiple end points is investigated that reduces the error for the estimation of maximum delay, demonstrated for a unit delay model and certain bit-lengths of Kogge-Stone adder.

Novel PVT Resilient Low-Power Dynamic XOR/XNOR Design Using Variable Threshold MOS for IoT Applications

A variable threshold voltage hybrid evaluation network based dynamic XOR/XNOR gate is presented to reduce the parameters leakage power dissipation, dynamic power, and layout area compared to existing dynamic gates under similar delay time conditions. This study explores the impacts of process, supply voltage, and temperature changes on leakage power dissipation and dynamic power using Monte Carlo simulation. The Monte Carlo analysis demonstrates that leakage power dissipation and dynamic power reduction have significantly improved. Furthermore, when compared to hybrid type dynamic XOR/XNOR (N-type XOR/XNOR), the proposed design reduces leakage power and dynamic power consumption by 6.1% (54.0%) and 18.75% (35.0%), respectively. While the proposed design has a slight layout area penalty compared to a hybrid type dynamic XOR/XNOR, it offers the same amount of the layout area as a traditional N-type XOR/XNOR.

Control of the coffee ring effect during R2R gravure printing for minimizing threshold voltage variation in printed carbon nanotube-based thin film transistors

Devising a high-throughput additive manufacturing method (HTAM) could aid in fabricating flexible electronic devices with marginal greenhouse gas (GG) emissions and net zero by-products. A roll-to-roll (R2R) gravure printing method is considered a typical platform of HTAM to fabricate carbon nanotube-based flexible electronic devices. However, the large variation in threshold voltage (Vth) in the printed carbon nanotube devices restricts device yield, thereby limiting their practical applications. In this study, the authors would like to show a way of minimizing the variation of Vth in the R2R gravure printed carbon nanotube thin-film transistors (TFTs) by understanding how the morphology of the printed dielectric layer can be controlled during ink drying. Since the formation of an uneven morphology after drying with higher edge thickness, also known as the coffee ring effect (CRE), is one of the key factors causing the variation in Vth, regulating the morphology of the dielectric ink is vital in minimizing the Vth variation of the TFTs printed via R2R gravure. By optimizing the rheological characteristics of the dielectric ink, a homogeneous morphology was attained without CRE, consequently minimizing the Vth variation from 19.6% to 6.9%. Furthermore, the printed device stability was improved by removing the CRE and avoiding the localized bias stress during device operation. Based on this work, the yield, and the stability of R2R gravure printed devices could be improved, enabling the rapid commercialization of additively manufactured flexible devices without the emission of GG or any harmful by-products.

P‐154: Late‐News Poster: High‐Performance Indium‐Gallium Oxide Thin‐Film‐Transistors via Plasma‐Enhanced Atomic‐Layer‐Deposition

We report the fabrication of high‐performance indium‐gallium oxide (IGO) thin‐film transistors (TFTs) via plasma‐enhanced atomic‐layer‐deposition (PE‐ALD) process with cation composition ratio variation. With accurate control of the composition ratio, IGO(12:3) TFTs showed stable characteristics along with high field‐effect mobility (μFET) of 70.69 cm 2 /Vs. Furthermore by increasing the gallium ratio, IGO(6:3) TFTs showed extremely stable characteristics with threshold voltage (VTH) variations lower than 0.1 V in both positive bias stress (PBS) and negative bias stress (NBS) conditions.

P‐23: Micro Light‐Emitting Diode Pixel Circuit Based on IGZO TFTs using a Stepwise Control Signal

We proposed an IGZO TFT‐based micro light‐emitting diode (μLED) pixel circuit using a stepwise control signal. The proposed pixel circuit expressed the gray levels by modulating the emission time with the constant driving current to suppress a wavelength shift of μLEDs. The proposed pixel circuit successfully expressed 8‐bit grayscale using a quaternary digital driving. The simulated μLED current waveforms showed a delay time of approximately 2 μs. Furthermore, the proposed circuit exhibited a luminance error rate below 5% under a threshold voltage variation of ±1 V.

7‐2: A Low‐Power Pixel Circuit Using Additional Current Path For Mini‐LED Displays

A novel structure with an additional current path is adopted in the proposed circuit to reduce the power consumption. Threshold voltage variations of TFTs and VDD I‐R drops are compensated effectively. The power consumption is reduced by 12.95% greater than the compared circuit without the additional current source structure.

Performance Analysis of Variable Threshold Voltage (ΔVth) Model of Junction less FinTFET

The work presented in this paper is a variable threshold voltage (ΔVth) model of junction less fin gate tunnel FET (JL FinTFET) in which there is a shift in threshold voltage. As a result, to improve drive current and subthreshold slope among other devices. At the same time, gradually decrease the random dopant fluctuations (RDF) effects on Vth, ambipolar leakage current by using this design. The threshold voltage in the junction less fin gate TFET may be modified using 2D numerical simulations by supplying a voltage to the variable gate. The effects of the threshold voltage change on the device's overall performance investigate. A GaSb junction less fin gate TFET and AlGaSb junction less fin gate TFETs with variable threshold voltage characteristics compare. The ON state current is 1.5x10-3 A/m, the SS is 17.1 mV/decade, and the Iamb is 3.314x10-17 A/m.