Threshold Voltage Tuning Research Articles

Implementation of floating gate MOSFET in inverter for threshold voltage tunability

This paper presents the ability of floating gate MOSFET (FGMOS) threshold voltage to be programmed or tuned which is exploited to improve the performance of electronic circuit design. This special characteristic owns by FGMOS is definitely contributes towards low voltage and low power circuit design. The comparison of threshold voltage between FGMOS and conventional NMOS is done in order to prove that FGMOS is able to produce a lower threshold voltage compared to conventional NMOS. In addition, in this paper, an implementation of FGMOS into inverter circuit is also done to show the programmability of FGMOS threshold voltage. The operations of the inverter circuits are verified using Sypnopsys simulation in 0.1μm CMOS technology with supply voltage of 1.8V.

Two methods of tuning threshold voltage of bulk FinFETs with replacement high-k metal-gate stacks

In this work, we propose two threshold voltage (VTH) tuning methods for bulk FinFETs with replacement high-k metal gate. The first method is to perform a vertical implantation into fin structure after dummy gate removal, self-aligned forming halo & punch through stop pocket (halo & PTSP) doping profile. The second method is to execute P+/BF2+ ion implantations into the single common work function (WF) layer in N-/P-FinFETs, respectively. These two methods have been investigated by TCAD simulations and MOS-capacitor experiments respectively, and then integrated into FinFET fabrication successfully. Experimental results show that the halo & PTSP doping profile can reduce VTH roll off and total variation. With P+/BF2+ doped WF layer, the VTH-sat shift −0.43V/+1.26V for N-FinFETs and −0.75V/+0.11V for P-FinFETs, respectively, with gate length of 500nm. The proposed two methods are simple and effective for FinFET VTH tuning, and have potential for future application of massive production.

Threshold Voltage Tuning Technique in Gate-All-Around MOSFETs by Utilizing Gate Electrode With Potential Distribution

A technique for achieving tunable threshold voltage ( $\text{V}_{\mathrm{ TH}})$ is investigated in a gate-all-around device, which is a representative floating body structure. For this concept, the in-plane gate is designed to be both a driving gate and a control gate. The control gate governs the potential distribution along the gate electrode, which acts as a built-in voltage divider in the MOSFET. During the $\text{V}_{\mathrm{ TH}}$ tuning by the control gate, there is no electrical performance degradation, and modulation of $\text{V}_{\mathrm{ TH}}$ follows a nearly perfect linear tendency. The results are verified by the electrical measurements of the fabricated device and a multi-physics simulator.

Analytical modeling and numerical simulation of novel double-gate InGaAs vertical nanowire transistor device for threshold voltage tuning and improved performance

This paper proposes a novel cylindrical double gate In0.53Ga0.47As vertical Nanowire n type device, which offers a higher drive current, better channel potential controllability and reduced short channel effects at ultra-short channel length 14nm through numerical simulation approach. An independent inner gate control is used for threshold voltage tuning. Improvement of drive current in the Double-Gate Vertical Nanowire Transistor (DG-VNWT) structure is achieved by growing the In0.53Ga0.47As Nanowire vertically on silicon substrate. Further to reduce the leakage current of the structure, we propose high-k LaAlO3 outer gate stack in integration with Al2O3 passivation layer and WN metal gate for the first time. Variable threshold voltage tuning is also achieved by inner gate control of the proposed device. An analytical model is built for validating threshold voltage dependence on inner gate voltage. Our results of the analytical model are observed to be at par with TCAD simulations. The proposed DG-VNWT device is compatible with silicon and high-k/metal gate CMOS technology with the unique capability of inner and outer gate control, the most promising scalable candidate for low power applications.

Step buffer layer of Al0.25Ga0.75N/Al0.08Ga0.92N on P-InAlN gate normally-off high electron mobility transistors

Normally-off AlGaN/GaN high electron mobility transistors (HEMTs) are indispensable devices for power electronics as they can greatly simplify circuit designs in a cost-effective way. In this work, the electrical characteristics of p-type InAlN gate normally-off AlGaN/GaN HEMTs with a step buffer layer of Al0.25Ga0.75N/Al0.1Ga0.9N is studied numerically. Our device simulation shows that a p-InAlN gate with a step buffer layer allows the transistor to possess normally-off behavior with high drain current and high breakdown voltage simultaneously. The gate modulation by the p-InAlN gate and the induced holes appearing beneath the gate at the GaN/Al0.25Ga0.75N interface is because a hole appearing in the p-InAlN layer can effectively vary the threshold voltage positively. The estimated threshold voltage of the normally-off HEMTs explored is 2.5 V at a drain bias of 25 V, which is 220% higher than the conventional p-AlGaN normally-off AlGaN/GaN gate injection transistor (GIT). Concurrently, the maximum current density of the explored HEMT at a drain bias of 10 V slightly decreases by about 7% (from 240 to 223 mA mm−1). At a drain bias of 15 V, the current density reached 263 mA mm−1. The explored structure is promising owing to tunable positive threshold voltage and the maintenance of similar current density; notably, its breakdown voltage significantly increases by 36% (from 800 V, GIT, to 1086 V). The engineering findings of this study indicate that novel p-InAlN for both the gate and the step buffer layer can feature a high threshold voltage, large current density and high operating voltage for advanced AlGaN/GaN HEMT devices.

Investigation of spatial charge distribution and electrical dipole in atomic layer deposited Al2O3 on 4H-SiC

Charge distribution and electrical dipole in an Al2O3/4H-SiC structure are investigated by capacitance–voltage measurement and x-ray photoelectron spectroscopy (XPS). The charge densities in Al2O3 and at the Al2O3/4H-SiC interface are negligible and −6.89 × 1011 cm−2, respectively. Thus the small charge amount indicates the suitability of Al2O3 as a gate dielectric. The dipole at the Al2O3/4H-SiC interface is −0.3 to −0.91 V. The XPS manifests electron transfer from Al2O3 to 4H-SiC. The dipole formation is explained by a gap state model and the higher charge neutrality level of Al2O3 than the Fermi level of 4H-SiC, which confirms the feasibility of the gap state model on investigating band lineup at heterojunctions. The electrical dipole at the Al2O3/4H-SiC interface is critical for threshold voltage tuning. These results are helpful in engineering the SiC based gate stacks.

Threshold Voltage Tuning in a-IGZO TFTs With Ultrathin SnOxCapping Layer and Application to Depletion-Load Inverter

Tunable threshold voltage of a thin-film transistor (TFT) is highly desirable for designing multifunctional electronic circuits. In this letter, an ultrathin SnO x capping layer was adopted to modify the threshold voltage of bottom-gate amorphous indium–gallium–zinc-oxide (a-IGZO) TFTs. A threshold voltage shift from 15.2 to −9.0 V was observed as the SnO x thicknesses increased from 0 to 19 nm, accompanying by a sizable increase of the intrinsic electron concentration in the channel layer. It was believed that the SnO x capping layer can extract loosely bound oxygen from the a-IGZO, which was supported by the SnO x composition variation with its thickness. Combining an uncovered a-IGZO TFT with a SnO x capped a-IGZO TFT, an enhancement/depletion inverter with a voltage gain of up to 45.9 was successfully demonstrated.

Tunable Graphene-GaSe Dual Heterojunction Device.

A field-effect device based on dual graphene-GaSe heterojunctions is demonstrated. Monolayer graphene is used as electrodes on a GaSe channel to form two opposing Schottky diodes controllable by local top gates. The device exhibits strong rectification with tunable threshold voltage. Detailed theoretical modeling is used to explain the device operation and to distinguish the differences compared to a single diode.

Double-gate SnO2 nanowire electric-double-layer transistors with tunable threshold voltage

Double-gate Sb-SnO2 nanowire electric-double-layer (EDL) transistors with in-plane gates were fabricated using only one shadow mask. The threshold voltage of such devices can be tuned in a wide range from −0.13 V to 0.72 V by the in-plane gate, which allows the device to switch from depletion-mode to enhancement-mode operation. The operation voltage of the double-gate device is 1 V because the EDL gate dielectric can lead to a high gate capacitance (>3.5 μF/cm2). Moreover, all double-gate devices show good electrical characteristics with high field-effect mobility (>200 cm2/V·s), high drain-current Ion/off ratio (>7 × 104), and small subthreshold slope (<100 mV/dec). These double-gate nanowire EDL transistors can pave the way for an electrically working low-voltage nano-electronic process.

Lanthanum quantification for optimization of advanced high-k/metal gate stacks using low energy electron x-ray emission spectrometry

The authors report about accurate monitoring of ultralow La doses inserted in advanced high-k/metal gate stacks for threshold voltage tuning purposes. Three characterization techniques are implemented for precise and reproducible lanthanum quantification. Low energy electron x-ray emission spectrometry capabilities are highlighted in terms of sensitivity and accuracy, thanks to a comparison with reference results obtained by Rutherford Backscattering Spectrometry. The capabilities of state-of-the-art Auger nanoprobes for depth profiling in the subnanometer range are also illustrated.

Tunable threshold voltage in solution-processed single-walled carbon nanotube thin-film transistors

We have investigated tunable threshold voltage in solution-processed single-walled carbon nanotube thin-film transistors (SWCNT TFTs) employing a simple and reproducible method of chemical encapsulation. Compared to a pristine one, SWCNT TFTs encapsulated with ammonium hydroxide (NH4OH) and nitric acid (HNO3) exhibit a negative shift and a positive shift in threshold voltage, respectively. Such results can be explained by the modification of the energy band at the interface between the source metal electrode and the SWCNT network. By using the Y-function method, we also characterized electrical properties such as field-effect mobility, threshold voltage, and contact resistance for TFTs treated with NH4OH or HNO3. The technique to favorably tune threshold voltage in solution-processed SWCNTs is significant for constituting CNT-based nanoelectronics.

Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process

In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300 mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f) noise. The measurement results show that the fabricated V-MOSFETs with 60 nm silicon pillar and 100 nm gate length achieve excellent steep sub-threshold swing (69 mV/decade for n-type and 66 mV/decade for p-type), good on-current (281 µA/µm for n-type 149 µA/µm for p-type), low off-leakage current (28.1 pA/µm for n-type and 79.6 pA/µm for p-type), and excellent on–off ratio (1 × 107 for n-type and 2 × 106 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (Vth) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control Vth more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise ( of 10−13–10−11 µm2/Hz for n-type and 10−12–10−10 µm2/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.

Top-gate organic depletion and inversion transistors with doped channel and injection contact

Organic field-effect transistors constitute a vibrant research field and open application perspectives in flexible electronics. For a commercial breakthrough, however, significant performance improvements are still needed, e.g., stable and high charge carrier mobility and on-off ratio, tunable threshold voltage, as well as integrability criteria such as n- and p-channel operation and top-gate architecture. Here, we show pentacene-based top-gate organic transistors operated in depletion and inversion regimes, realized by doping source and drain contacts as well as a thin layer of the transistor channel. By varying the doping concentration and the thickness of the doped channel, we control the position of the threshold voltage without degrading on-off ratio or mobility. Capacitance-voltage measurements show that an inversion channel can indeed be formed, e.g., an n-doped channel can be inverted to a p-type inversion channel with highly p-doped contacts. The Cytop polymer dielectric minimizes hysteresis, and the transistors can be biased for prolonged cycles without a shift of threshold voltage, indicating excellent operation stability.

Improvement of negative-bias-illumination-stress stability in all-transparent double-gate InGaZnO thin-film transistors

Fully transparent amorphous-InGaZnO thin-film transistors (TFTs) with double-gate (DG) configuration were fabricated. Both top-gate and bottom-gate (BG) TFT fabricated with a single gate-stack structure were found to exhibit sound device characteristics with μsat of 17.0 and 18.1 cm2 V−1 s−1, respectively. Confirmed benefits of DG configuration include improved current drivability and threshold voltage tunability. Further, controlling the fixed voltage bias to the BG was observed to enhance device stability under negative-bias-illumination-stress conditions.

Threshold voltage tuning and printed complementary transistors and inverters based on thin films of carbon nanotubes and indium zinc oxide

Carbon nanotubes (CNTs) have emerged as an important material for printed macroelectronics. However, achieving printed complementary macroelectronics solely based on CNTs is difficult because it is still challenging to make reliable n-type CNT transistors. In this study, we report threshold voltage (Vth) tuning and printing of complementary transistors and inverters composed of thin films of CNTs and indium zinc oxide (IZO) as p-type and n-type transistors, respectively. We have optimized the Vth of p-type transistors by comparing Ti/Au and Ti/Pd as source/drain electrodes, and observed that CNT transistors with Ti/Au electrodes exhibited enhancement mode operation (Vth 0). For example, an In:Zn ratio of 2:1 yielded an enhancement mode n-type transistor with Vth ~ 1 V and Ion of 5.2 μA. Furthermore, by printing a CNT thin film and an IZO thin film on the same substrate, we have fabricated a complementary inverter with an output swing of 99.6% of the supply voltage and a voltage gain of 16.9. This work shows the promise of the hybrid integration of p-type CNT and n-type IZO for complementary transistors and circuits.

Aligned Polythiophene and its Blend Film by Direct‐Writing for Anisotropic Charge Transport

A combination of patterning and film alignment techniques helps to build multi‐order polymer architecture for application in flexible electronics. A direct‐writing method is employed using microcapillary arrays to prepare semiconducting polymer films with both optical and electrical anisotropy. Not only aligned poly(3‐butylthiophene) (P3BT) nanowires in neat P3BT films, but also aligned P3BT nanowires within a polystyrene (PS) matrix are obtained, which yields an aligned semiconductor/insulator polymer blend with anisotropic charge transport. The field‐effect transistor (FET) mobilities/threshold voltages from both vertical and parallel to alignment directions as well as their dependence on blending ratio are studied. The increased mobility of P3BT/PS blends, as compared with neat P3BT, is observed in both vertical and parallel directions. Using this alignment method, FET mobility and threshold voltage of the semiconductor/insulator polymer blends are comprehensively tuned, from which a digital inverter with gain up to 80 is realized. Therefore, this work not only helps understanding the charge transport mechanism in semiconducting/insulating polymer blends, but also provides an effective approach towards high‐performance field‐effect transistors with tunable mobility and threshold voltage.

Tunable threshold voltage of an n-type Si nanowire ferroelectric-gate field effect transistor for high-performance nonvolatile memory applications

We successfully fabricated ferroelectric-gate field effect transistor (FEFET)-based nonvolatile memory devices using an n-type Si nanowire coated with omega-shaped-gate organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) via a low-temperature fabrication process. Our FEFET memory devices with controllable threshold voltage via adjustment of the doping concentration exhibit excellent memory characteristics with ultra-low ON state power dissipation (≦̸3 nW), a large modulation in channel conductance between the ON and OFF states exceeding 105, a long retention time of over 3 × 104 s and a high endurance of over 105 programming cycles whilst maintaining an ION/IOFF ratio higher than 103. This result may be promising for next-generation nonvolatile memory on flexible substrate applications.

Integration of Advanced MOSFET Device with Dual Effective Band Edge Work Function Metals Using Both HK and MG Last Scheme

The aggressive downscaling of CMOS requires both lateral and vertical shrinkage of dimensions. SiO2 served as gate dielectrics for more than four decades now is with severe leakage problem with quantum mechanical tunneling effect due to SiO2has been scaled down to only a few atomic layers to boost device performance. Thus high dielectric constant materials such as Hafnium oxide and Hafnium silicate are of great interests in recent years [1]-[3]. Meanwhile HK layers are not perfectly compatible with silicon channel surface as traditional silicon dioxide due to interface trap, dipole and defect are formed during processing which would be difficult for threshold voltage tuning. Gate stacks engineering like interfacial layer, post dielectric anneal and metal gate are needed to be carefully handled to alleviate these side effects. Due to excellent EOT scaling and short channel effect controllability, HKMG has been implemented into modern bulk silicon device to replace traditional Poly/SiON process. Different from Poly/SiON process which poly gate can be doped with N type and P type dopants respectively for NFET and PFET threshold voltage adjustment, Metal gate last process integration needs two kinds of metal to tune MOSFET work function in order to achieve suitable device performance [4, 5]. In this work, we have successfully fabricated devices with dual effective work function metals with 4.15eV and 5.04eV for NFET and PFET respectively. With EWF close to band edge, threshold voltage can be effectively achieved with 0.35V and -0.31V for NFET and PFET respectively. Process conditions and electrical results are also discussed.TiN served as PMOS work function metal and TiAl chosen as NMOS work function metal are integrated into CMOS. The detail integration flow of HKMG and TEM of cross section of gate structure are shown in Figure.1.In Fig. 2, threshold voltages with different Al% concentration are plotted. It can be shown that threshold voltage is strongly dependent on Al atomic concentration. With more percentage of concentration of Al, Vt would be lower due to work function Fermi level close to conduction band edge. Table.1 shows the effective work function values for NFET and PFET respectively. The EWFs are both close to band edges which are suitable for Vt tuning for devices. Fig.3 shows the NFET and PFET Id-Vg curves with low DIBL and sub-threshold swing performance. DIBL can be as low as 78mV/V and 82mV/V for NFET and PFET respectively. Swing can be as low as 62mV/dec and 64mV/dec for NFET and PFET respectively. It effectively demonstrates that controllability for metal gate to channel is much better comparing with Poly/SiON gate stackIn conclusion, we have successfully fabricated NFET and PFET devices with both HK and MG last integration scheme. By optimizing process conditions, Both NFET and PFET effective work functions can be tuned to be close to band edges with TiAl as NFET work function metal and TiN as PFET work function metal. Al concentration impaction on Vt is analyzed. Vt are well controlled with different channel length. DIBL and Swing are as low as to 78mV/V and 82mV/V and 62mV/dec and 64mV/dec for NFET and PFET respectively.

High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage.

We successfully fabricated nanowire-based complementary metal-oxide semiconductor (NWCMOS) inverter devices by utilizing n- and p-type Si nanowire field-effect-transistors (NWFETs) via a low-temperature fabrication processing technique. We demonstrate that NWCMOS inverter devices can be operated at less than 1 V, a significantly lower voltage than that of typical thin-film based complementary metal-oxide semiconductor (CMOS) inverter devices. This low-voltage operation was accomplished by controlling the threshold voltage of the n-type Si NWFETs through effective management of the nanowire (NW) doping concentration, while realizing high voltage gain (>10) and ultra-low static power dissipation (≤3 pW) for high-performance digital inverter devices. This result offers a viable means of fabricating high-performance, low-operation voltage, and high-density digital logic circuits using a low-temperature fabrication processing technique suitable for next-generation flexible electronics.

Quasi-double gate regime to boost UTBB SOI MOSFET performance in analog and sleep transistor applications

This paper investigates both electrostatic control improvement and performance enhancement of UTBB SOI MOSFETs obtained in quasi-double-gate (QDG) regime (i.e. simultaneously biasing top- and back-gate (substrate or ground plane) as Vbg=k·Vg) as a strong function of k-multiplication factor, when compared to a standard single-gate mode. Improved performance (in terms of transconductance, drive current and early voltage) in QDG mode combined with lowered DIBL and enhanced gain are of interest for high-precision low-frequency analog applications. QDG mode is demonstrated to allow threshold voltage tuning, subthreshold swing reduction and on-current enhancement without off-state current degradation, thus of interest for digital applications. The unique feature of QDG mode is finally exploited to boost the performances of the sleep transistor in the practical use case of a power-gated processor. About 30% reduction of the leakage in stand-by mode is achieved at nominal Vg with a Vbg of 3V, which can be generated at marginal area/power overheads with an on-chip charge pump with an architecture proposed in this paper.