Quasi-double gate regime to boost UTBB SOI MOSFET performance in analog and sleep transistor applications

Abstract

This paper investigates both electrostatic control improvement and performance enhancement of UTBB SOI MOSFETs obtained in quasi-double-gate (QDG) regime (i.e. simultaneously biasing top- and back-gate (substrate or ground plane) as Vbg=k·Vg) as a strong function of k-multiplication factor, when compared to a standard single-gate mode. Improved performance (in terms of transconductance, drive current and early voltage) in QDG mode combined with lowered DIBL and enhanced gain are of interest for high-precision low-frequency analog applications. QDG mode is demonstrated to allow threshold voltage tuning, subthreshold swing reduction and on-current enhancement without off-state current degradation, thus of interest for digital applications. The unique feature of QDG mode is finally exploited to boost the performances of the sleep transistor in the practical use case of a power-gated processor. About 30% reduction of the leakage in stand-by mode is achieved at nominal Vg with a Vbg of 3V, which can be generated at marginal area/power overheads with an on-chip charge pump with an architecture proposed in this paper.