Threshold Voltage Of Transistors Research Articles

Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips

Aggressive power supply scaling into the near-threshold voltage (NTV) region holds great potential for applications with strict energy budgets, since the energy efficiency peaks as the supply voltage approaches the threshold voltage (VT) of the CMOS transistors. The improved silicon energy efficiency promises to fit more cores in a given power envelope. As a result, many-core Near-threshold computing (NTC) has emerged as an attractive paradigm. Realizing energy-efficient heterogenous system on chips (SoCs) necessitates key NTV-optimized ingredients, recipes and IP blocks; including CPUs, graphic vector engines, interconnect fabrics and mm-scale microcontroller (MCU) designs. We discuss application of NTV design techniques, necessary for reliable operation over a wide supply voltage range—from nominal down to the NTV regime, and for a variety of IPs. Evaluation results spanning Intel’s 32-, 22- and 14-nm CMOS technologies across four test chips are presented, confirming substantial energy benefits that scale well with Moore’s law.

Robust linear sampling switch for low-voltage SAR ADCs

This paper presents a linear sampling switch for low-voltage successive-approximation register (SAR) analogue-to-digital converters (ADCs) operating at a frequency of tens of MHz. The proposed switch employs a bootstrapped transmission gate, where the bulk voltages are generated internally to minimize variations in the threshold voltage of transistors with input signal amplitude. Thus, ensuring almost constant and low ON-resistance ($$R_{ON}$$) over complete input signal range without using wide transistors, charge pumps, or both, at low supply voltages. The proposed switch was designed using standard 65 nm CMOS technology. The post-layout simulations have shown a signal to noise and distortion ratio (SNDR) of 87.81 dB, a spurious-free dynamic range (SFDR) of 90 dB and a total harmonic distortion (THD) of $$-91.5\,\hbox {dB}$$ at a sampling frequency and supply voltage of 100 MHz and 0.8 V, respectively. In addition, the switch has shown a maximum variation of 1% in $$R_{ON}$$ over input signal amplitude at different process corners and temperature, which is low compared to other sampling switches reported in the literature.

Designing and Analysis of a Negative Bias Temperature Instability Sensing Circuit

Scale down the size of devices introduce the effect of negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and hot carrier injection (HCI) in very-large-scale integration (VLSI) chip design and the major concern is to minimize these effects to a nominal value. In the paper, authors focus in minimization of NBTI effect and develop a noble degradation monitoring sensor circuit named SCHIMOS. A comparison is stated between an analytically strong equisensitive LISOCHIN sensor and SCHIMOS in 90nm and 45nm technology node. Paper experimentally reduces the NBTI effect that is controlled by a number of factors including a reduction in PMOS size, duty cycle, and VDD-Vth tuning. However, NBTI effect degrades the speed and increases the threshold voltage of PMOS transistors. Keywords: NBTI, SCHIMOS, LISOCHIN, PMOS size, VDD-Vth tuning. Cite this Article: Deepjyoti Kalita, Partha Pratim Saikia, Debaprasad Das. Designing and Analysis of a Negative Bias Temperature Instability Sensing Circuit. Research & Reviews: A Journal of Embedded System & Applications. 2020; 8(1): 6–11p.

Soft error hardening enhancement analysis of NBTI tolerant Schmitt trigger circuit

Bias temperature instability (BTI) and soft errors are major reliability concerns for deep submicron technologies. Negative BTI leads to an increase of the threshold voltage of PMOS transistors and is thus considered a serious challenge for improving circuit performance. In this paper, we concentrate on a design-time solution, i.e., more reliable NMOS only Schmitt Trigger with Voltage Booster (NST-VB). For this we analyzed the impact of BTI on the soft-error susceptibility of different CMOS circuits using HSPICE and performed critical charge simulations considering different supply voltages and stress time. From our results, we conclude that the NST-VB circuit has a higher critical charge when compared to CMOS inverters and Schmitt trigger (ST) based counterparts. NST-VB has improved the sensitivity of 62.48% and 55.10%, as compared to CMOS inverter and ST circuits, respectively, after three years of operation. To better assess soft error resilience, we introduce a soft error rate ratio (SERR) as a performance metric. Our analysis indicates that NST-VB has 12.62%, and 12.39% less SERR compared to ST and CMOS inverters. The effect of process variation on CMOS inverter, ST inverter and NST-VB circuit are analyzed using 5000 Monte Carlo simulations for critical voltages and we observe that the deviation of NST-VB is 6.06× and 6.89× less as compared to the CMOS and ST based inverters, respectively.

A New Method for Defect Prediction of Polycrystalline Silicon TFTs with Realistic Grain Boundary Model

We investigate the deviation of threshold voltage (V<SUB>th</SUB>) of p-channel polycrystalline silicon thin film transistors (poly-Si TFTs) using a new GB (grain boundary) model that better reflects reality. And we proposed new method for defect prediction using by this new GB model. The new GB model reflects a gaussian distribution of grain size and GB position. And by introducing a new parameter (β) which represents the defect ratio between GB and grain, the Vth deviation that increases as the channel gets shorter can be matched with the actual measurement results. And we found that the increase in the Vth deviation in the short channel becomes larger as the number of defects increases in GB (as the β increases). And we found that the β is an important physical parameter to explain why the Vth deviation of the short channel is rapidly increased. In this way, using this β value in our GB model, it is possible to predict the relative density of defect states of GB in the poly-Si by monitoring the Vth deviation in short channel TFTs in the process of developing polycrystalline TFTs.

Examining the Electrical characteristic for Triple Material Double-Gate Silicon-On-Nothing (SON) MOSFETs with High Dielectric Oxide: A Comparative Study

Demand for devices with higher processing speed and lower power consumption increase exponentially every year. The device industry achieved these demands by the down-scaling device structures. As device size decreases, the physical parameters also decrease. This results in several critical issues. One such an issue is the decreasing of device threshold voltage. This decrease in threshold voltage is the result of decrease in control by the gate above the channel region and source/drain charge sharing. Silicon-on-nothing (SOI) and Silicon-on-insulator (SON) are among some structural solutions to tackle this issue. In this paper, studies on the effects of various physical parameters to the threshold voltage of a double-gate SON metal oxide semiconductor field-effect transistor (MOSFET) has been presented. The concept of high dielectric material on the oxide layer and gate material engineering is also incorporated. A comparison between SON and SOI is also carried out on the ATLAS simulator.

Ingress of Threshold Voltage-Triggered Hardware Trojan in the Modern FPGA Fabric–Detection Methodology and Mitigation

The ageing phenomenon of negative bias temperature instability (NBTI) continues to challenge the dynamic thermal management of modern FPGAs. Increased transistor density leads to thermal accumulation and propagates higher and non-uniform temperature variations across the FPGA. This aggravates the impact of NBTI on key PMOS transistor parameters such as threshold voltage and drain current. Where it ages the transistors, with a successive reduction in FPGA lifetime and reliability, it also challenges its security. The ingress of threshold voltage-triggered hardware Trojan, a stealthy and malicious electronic circuit, in the modern FPGA, is one such potential threat that could exploit NBTI and severely affect its performance. The development of an effective and efficient countermeasure against it is, therefore, highly critical. Accordingly, we present a comprehensive FPGA security scheme, comprising novel elements of hardware Trojan infection, detection, and mitigation, to protect FPGA applications against the hardware Trojan. Built around the threat model of a naval warship's integrated self-protection system (ISPS), we propose a threshold voltage-triggered hardware Trojan that operates in a threshold voltage region of 0.45V to 0.998V, consuming ultra-low power (10.5nW), and remaining stealthy with an area overhead as low as 1.5% for a 28 nm technology node. The hardware Trojan detection sub-scheme provides a unique lightweight threshold voltage-aware sensor with a detection sensitivity of 0.251mV/nA. With fixed and dynamic ring oscillator-based sensor segments, the precise measurement of frequency and delay variations in response to shifts in the threshold voltage of a PMOS transistor is also proposed. Finally, the FPGA security scheme is reinforced with an online transistor dynamic scaling (OTDS) to mitigate the impact of hardware Trojan through run-time tolerant circuitry capable of identifying critical gates with worst-case drain current degradation.

8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing

Large-scale digital computing almost exclusively relies on the von Neumann architecture, which comprises separate units for storage and computations. The energy-expensive transfer of data from the memory units to the computing cores results in the well-known von Neumann bottleneck. Various approaches aimed toward bypassing the von Neumann bottleneck are being extensively explored in the literature. These include in-memory computing based on CMOS and beyond CMOS technologies, wherein by making modifications to the memory array, vector computations can be carried out as close to the memory units as possible. Interestingly, in-memory techniques based on CMOS technology are of special importance due to the ubiquitous presence of field-effect transistors and the resultant ease of large-scale manufacturing and commercialization. On the other hand, perhaps the most important computation required for applications such as machine learning, etc., comprises the dot-product operation. Emerging nonvolatile memristive technologies have been shown to be very efficient in computing analog dot products in an in situ fashion. The memristive analog computation of the dot product results in much faster operation as opposed to digital vector in-memory bitwise Boolean computations. However, challenges with respect to large-scale manufacturing coupled with the limited endurance of memristors have hindered rapid commercialization of memristive-based computing solutions. In this paper, we show that the standard 8 transistor (8T) digital SRAM array can be configured as an analoglike in-memory multibit dot-product engine (DPE). By applying appropriate analog voltages to the read ports of the 8T SRAM array and sensing the output current, an approximate analog–digital DPE can be implemented. We present two different configurations for enabling multibit dot-product computations in the 8T SRAM cell array, without modifying the standard bit-cell structure. We also demonstrate the robustness of the present proposal in presence of nonidealities such as the effect of line resistances and transistor threshold voltage variations. Since our proposal preserves the standard 8T-SRAM array structure, it can be used as a storage element with standard read–write instructions and also as an on-demand analoglike dot-product accelerator.

Evolutionary Computation for Parameter Extraction of Organic Thin-Film Transistors Using Newly Synthesized Liquid Crystalline Nickel Phthalocyanine.

In this work, the topic of the detrimental contact effects in organic thin-film transistors (OTFTs) is revisited. In this case, contact effects are considered as a tool to enhance the characterization procedures of OTFTs, achieving more accurate values for the fundamental parameters of the transistor threshold voltage, carrier mobility and on-off current ratio. The contact region is also seen as a fundamental part of the device which is sensitive to physical, chemical and fabrication variables. A compact model for OTFTs, which includes the effects of the contacts, and a recent proposal of an associated evolutionary parameter extraction procedure are reviewed. Both the model and the procedure are used to assess the effect of the annealing temperature on a nickel-1,4,8,11,15,18,22,25-octakis(hexyl)phthalocyanine (NiPc6)-based OTFT. A review of the importance of phthalocyanines in organic electronics is also provided. The characterization of the contact region in NiPc6 OTFTs complements the results extracted from other physical–chemical techniques such as differential scanning calorimetry or atomic force microscopy, in which the transition from crystal to columnar mesophase imposes a limit for the optimum performance of the annealed OTFTs.

A Bit-Line Voltage Sensing Circuit With Fused Offset Compensation and Cancellation Scheme

A systematic offset voltage occurs in sense amplifiers for SRAMs, mainly due to the mismatch between the threshold voltages of MOS transistors. This offset affects the reading operations of SRAMs in terms of accuracy, delay and power consumption. In this brief, a bit-line voltage sense amplifier is presented, which combines offset compensation and cancellation features. The circuit operations are carried out in four phases, in which two CMOS amplifiers are used as line buffers and they are pre-charged in the high voltage gain region in order to reduce the effects of the offset. The proposed sense amplifier has been designed and prototyped in 180-nm CMOS technology. It is capable to correct a voltage offset up to 100 mV and exhibits a minimum access time of 58 ps. These results overcome other solutions in applications where sub-threshold operations are not required and an aggressive voltage scaling is not convenient.

PHYSICS OF NANOTRANSISTORS: 2D MOS ELECTROSTATICS AND VIRTUAL SOURCE MODEL

In the fourth one from the line our new tutorial reviews, directed to serve students, university teachers and researchers, the 2D electrostatics of MOS is considered in detail. It is demonstrated, that 2D electrostatics degrades electron transport in field effect transistors by increasing the subthreshold swing and causing the DIBL effect, which in its turn increases the output conductivity and reduces the threshold voltage in short-channel transistors. Since these effects are more pronounced in short-channel transistors, they are also called short channel effects. As transistors get smaller and smaller, the main challenge with circuitry is to control the short-channel effects. As a rule, numerical modeling is required.

Simulation of Structure Parameters' Influence on the Threshold Voltage of Normally‐Off p‐GaN/AlGaN/GaN Transistors

The influence of different parameters of p‐GaN/AlGaN/GaN structure on a threshold voltage of transistors is studied. The parameters that are varied are the thickness of the p‐type GaN layer, its doping concentration, doping concentration of the GaN channel layer, and Schottky barrier height. Increasing the thickness of the p‐GaN layer is found to increase the threshold voltage. Also, increasing doping concentration of the p‐GaN layer increases the threshold voltage. The doping concentration of the GaN channel layer has the decisive effect on the possibility to use capacitance measurement for the threshold voltage assessment. Simulations show an interesting result of the Schottky barrier height threshold voltage dependence. For higher Schottky barrier height, lower threshold voltage is received, which is connected with the contribution of the negative differential capacitance of the p‐GaN layer. This starts to increase for higher positive voltage if the Schottky barrier height is lower.

Consequences of Body-Biasing Technique on SRAM Memory

The circuit changes the threshold voltage effectively with a definite delay and power by altering the body biasing of the transistors. The body bias is employed to govern the frequency and leakage of the memory device. The threshold voltage of individual transistor is decreases by applying the reverse body bias (RBB) and increases with forward body bias (FBB). This paper presents the viability of RBB to decrease the leakage power and increase in the speed of operations for SRAM circuit. The investigation of RBB dependencies on various performance parameters are analyzed. It is observed that the leakage power improves by 30.32% on applying RBB voltage compared to zero body bias while the transient power increases by 3.22% but decrease of delay by 84.56% dominates on it. Because of this the overall energy consumption reduces by 84.06%. Further the simulation work is carried out to see effect of supply voltage variation on leakage power at different RBB voltage and temperature. Therefore, the RBB scheme is beneficial for devices of low leakage, low energy and high speed of operation but this RBB voltage is limited by band-to-band tunneling current.

2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage Variations

A 2[Formula: see text]VDD CMOS output buffer with process, voltage and leakage (PVL) detection mechanism is proposed such that slew rate is auto-adjusted to reduce the variations at different corners. To boost the driving current, low threshold voltage transistors are used instead of devices with typical threshold voltage in the driving transistor of output stage. More importantly, to prevent large leakage of those large low threshold voltage devices, leakage detection resistors are added at the gates of the always-on low threshold voltage transistors to clamp the leakage. The static power consumption is reduced when it is not activated. Another feature of the proposed design is that the gate-oxide leakage is also reduced by lengthening the driving transistors. Besides, all biases in the proposed design are generated from bandgap circuits such that not only is the variation caused by temperature drifting reduced, the area overhead and power dissipation are also minimized. The proposed design is carried out by using 28-nm CMOS process. The data rate proved by physical measurement is proved to be 2.0[Formula: see text]GHz given 1.8/1.05[Formula: see text]V supply voltage, namely, VDD or 2[Formula: see text]VDD, when the proposed PVL detection as well as the compensation circuitry are activated.

Stability analysis of Sub-threshold 6T SRAM cell at 45 nm for IoT application

In ultra-Low power application the supply volt- age in the circuit is as minimum as possible to correct perform the operation. Reducing the supply voltage below the threshold Voltage of transistor is known as sub threshold voltage that affects the delay as well as stability parameter of the Circuit. In this paper body biased technique is applied at standard 6T SRAM which improve the static Current Noise Margin(SINM) and Write trip Current by the factor of 4.15 times and 4.7 times respectively from the Conventional (conv) 6T SRAM. SINM defined the read stability whereas WTI are write ability Parameters of the circuit. In the Sub threshold region delay parameter of the circuit increased, but in this paper delay and power of the proposed circuit are going to be degrades 2.34 times and 4.39 times from the conv. 6T SRAM at different Process Corner i.e. the Performance of the device get increased. In this paper conventional (Conv.)6T and Proposed(PP) 6T both have same W/L ratio at supply voltage of 400mv.

NBTI stress delay sensitivity analysis of reliability enhanced Schmitt trigger based circuits

Negative Bias Temperature Instability (NBTI) in PMOS transistors results in increased transistor threshold voltage, is considered the major contributor to circuit performance degradation and to alleviate its effect appropriate design and lifetime measures are required. In this paper, we concentrate on a design-time solution, i.e., the replacement of CMOS inverters by more reliable counterparts, i.e., Schmitt Trigger (ST) and NMOS only Schmitt Trigger with Voltage Booster (NST-VB). We first compare the three candidates implemented in 32 nm CMOS technology concerning delay variation. Our results indicate that, after three years of NBTI stress, NST-VB exhibits an almost negligible delay shift of 0.47%, while ST and CMOS inverter experience a delay shift of 7.2% and 5.32%, respectively. Subsequently, we extend the scope and assume the ISCAS’89 s27 circuit as a discussion vehicle. Our evaluations indicate that after 3-year stress time, the critical path delay of the s27 CMOS, ST, and NST-VB based implementations increases by 105.1 ps, 185.2 ps, and 94.2 ps, respectively. To put things into a better perspective, we introduce the Inverse Power Area Reliability Product (IPARP) as compound reliability metric. Our analysis indicates that the normalized IPARP values for ST and NST-VB implementations are 0.062 and 1.903, respectively, compared to CMOS implementation.

Gamma-ray irradiation effects on the electrical properties of organic field-effect transistors

We investigated the changes in the organic transistor characteristics of poly(3-hexylthiophene-2,5-diyl) (P3HT) and phenyl-C61-butyric acid methyl ester (PCBM) thin films upon high-energy gamma-ray irradiation. Devices based on both organic semiconductors showed a lower field-effect mobility and electrical current levels after gamma-ray irradiation. The threshold voltage of P3HT transistors shifted negative, while that of PCBM-based devices shifted positive. These changes in electrical performance of the devices can be utilized as a gamma-ray sensing elements.

Defects induced by gamma-ray irradiation and post-irradiation annealing and its influence on the threshold voltage of p-channel power VDMOS transistors

ABSTRACTThe investigations presented here study the creation as well as passivation/neutralization of positive trapped charge in the oxide (fixed traps) and traps near and at the Si–SiO2 interface (switching traps) exposed to gamma-ray irradiation and subsequent annealing (at room temperature and late at 150°C) in commercial p-channel power Vertical Double Diffused Metal-Oxide-Semiconductor transistors. The separation of fixed and switching traps that contributes to the threshold voltage shift was carried out using the midgap-subthreshold method. It was shown that fixed traps creation is a dominant process during irradiation. Subsequent postirradiation annealing at room temperature, without gate bias, was performed for , i.e. 19.4 days and it further lead to a relatively small change in , induced by a decrease in fixed traps density and an increase in switching traps density. The experimental results have revealed the existence of latent switching traps build-up during continued annealing at 150°C with +10 V gate bias. At latter annealing times, the switching traps passivation becomes the dominant process. In order to explain these experimental results, we have used models that include processes of creation and passivation of fixed and switching traps during irradiation and annealing. The possible application of these components in gamma-ray dosimetry was also analysed.

A CMOS RF Energy Harvester With 47% Peak Efficiency Using Internal Threshold Voltage Compensation

This letter presents a dual-band (0.902 and 2.45 GHz) radio frequency (RF)–dc CMOS converter employing the internal threshold voltage cancelation (IVC) technique to harvest electromagnetic energy. The realized RF–dc CMOS converter maintains high power conversion efficiency (PCE) by passively reducing the threshold voltage of the forward-biased transistors so as to increase the harvested power, and increases the threshold voltage of the reverse-biased transistors to reduce the leakage current. More than 20% measured PCE is achieved at 0.902 GHz from −9 to 10-dBm input power range and a peak PCE of 47% is obtained at 1 dBm. At 2.45-GHz band, more than 11% measured PCE is achieved from −2 to 15 dBm input power range and a peak PCE of 27.1% is obtained at 6 dBm. A single-stage RF–dc CMOS converter is realized in 180-nm CMOS technology and it can serve as a good reference to multiband CMOS energy harvesting design in the future.

Effect of Substrate Induced Surface Potential (SISP) on Threshold Voltage of SOI Junction-Less Field Effect Transistor (JLFET)

In the present paper, a threshold voltage model of short channel silicon-on-insulator (SOI) Junctionless Field Effect Transistors (JLFETs) has been presented. The model includes the effect of substrate-induced surface potential (SISP) effect on threshold voltage with necessary changes in the boundary conditions at the silicon-buried oxide (BOX) interface. Such changes render difference in potential between substrate bulk and surface. The channel potential has been modelled using the parabolic approximation method. The developed model is useful for the optimization of short-channel effects for SOI JLFETs. The substrate bias voltage as a fourth terminal is found to be a powerful tool for tuning the threshold voltage for different device parameters variation. The model results are in good agreement with the simulation results obtained from Sentaurus TCAD simulator.