Threshold Voltage Of Transistors Research Articles

Novel Radiation Hardened SOT-MRAM Read Circuit for Multi-Node Upset Tolerance

The rapid transistor scaling and threshold voltage reduction pose several challenges such as high leakage current and reliability issues. These challenges also make VLSI circuits more susceptible to soft-errors, particularly when subjected to harsh environmental conditions. Hybrid spintronic/CMOS technology has emerged as one of the promising techniques to achieve low leakage power and non-volatility. Moreover, the spintronic memories are inherently resistant to the radiation effects such as heavy-ion irradiation and total ionizing dose. However, its CMOS peripheral circuitry is more susceptible to radiation-induced single-event upset (SEU) and double-node upset (DNU). In this paper, a new radiation-hardened read circuit for SOT magnetic random access memory (MRAM) on 45nm technology has been presented. The proposed circuit is highly resistant to all the probable SEUs and DNUs when compared to the previously reported designs. The results show that it can tolerate 4.5X, 11X, 9X, and 10.5X more critical charge as compared to the cross-coupled CMOS transistor, 11T, 13T, and 11T radiation hardened circuits, respectively. Moreover, the recovery time of the proposed circuit is improved by 20% when compared to cross-coupled CMOS transistor circuits.

A High-Sensitivity Wide Input-Power-Range Ultra-Low-Power RF Energy Harvester for IoT Applications

Radio frequency energy harvesting (RFEH) is very attractive for the Internet of things (IoT) and self-powered micro-systems such as wearable biomedical devices and wireless sensor networks. This paper proposes, analyzes, and implements a new RF-DC converter in standard 130 nm CMOS technology. The developed converter is designed and optimized for ultra-low-power IoT and wearable biomedical applications using the 900 MHz ISM band. The proposed 10-stage cross-connected rectifier compensates the transistors threshold voltage by using both dynamic and static bias compensation techniques. An analytical model of the rectifier based on the MOSFET transistor equations is presented, allowing optimization of the rectifier as a function of the number of stages and transistors sizing, improving the sensitivity and the input power range of the converter. The measurement results demonstrate a sensitivity of &#x2212;25.5 dBm for 1 V output across a 5-<inline-formula> <tex-math notation="LaTeX">$\text{M}\Omega $ </tex-math></inline-formula> resistive load and &#x2212;29 dBm for a 100 <inline-formula> <tex-math notation="LaTeX">$\text{M}\Omega $ </tex-math></inline-formula> load, which is better than the best previously reported results. The measured peak end-to-end efficiency of the proposed harvester is 42.4&#x0025; at &#x2212;16 dBm input power, delivering 2.19 V to a 450 <inline-formula> <tex-math notation="LaTeX">$\text{k}\Omega $ </tex-math></inline-formula> load.

Ultra-Low-Voltage UTBB-SOI-Based, Pseudo-Static Storage Circuits for Cryogenic CMOS Applications

Operating CMOS circuits at cryogenic temperatures offers advantages of higher mobility, higher ON-current, and better subthreshold characteristics, which can be leveraged to realize high-performance CMOS circuits. However, an ultra-low-voltage operation is necessary to minimize the power consumption and to offset the cooling cost overheads. The MOSFET threshold voltages (Vt) increase at cryogenic temperatures making it challenging to achieve high performance while operating at very low voltage. Ultra-thin body and buried oxide silicon-on-insulator (UTBB-SOI)-based MOSFETs can modulate the transistor threshold voltage using the back-gate bias, unlike conventional FinFETs. This unique UTBB-SOI technology attribute has been leveraged to realize compact pseudo-static storage circuits, namely, embedded dynamic random access memory (DRAM) bitcell and a flip-flop operating at 0.2 V and 77 K. This article presents UTBB-SOI device fabrication details and calibrate experimental device characteristics with BSIM compact models. SPICE simulations suggest the feasibility of three-transistor gain-cell embedded DRAM (eDRAM) capable of reliably storing three distinct voltage levels (1.5 bits/cell) and exhibiting retention time of the order of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s. Furthermore, a unique pseudo-static flip-flop design is presented, which can lower the clock power by 50%, transistor count by 20%, and static power consumption by 20%.

Feasibility Study of Tuning the Threshold Voltage of Nanoscale Fin-shaped Field Effect Transistor (FinFET) via Metal Gate Workfunction Engineering

Feasibility Study of Tuning the Threshold Voltage of Nanoscale Fin-shaped Field Effect Transistor (FinFET) via Metal Gate Workfunction Engineering

Conditions for the identical distribution of free carriers in thin films

The condition of the same distribution of free carriers in thin films is necessary for comparing the mobility and analyzing the scattering mechanisms of carriers near semiconductor film/insulator interfaces. In thin film/insulator systems with different design parameters, it is difficult to ensure the same distribution of free carriers due to physical phenomenon such as the coupling effect. In this study, TCAD simulations of thin-film transistors, which have been used to monitor Si film properties, were applied to find parameters that allow tuning the potential distribution and, accordingly, the distribution of free carriers in films. It was found that such parameters are the film regime, the density of induced carriers, the gate voltage or threshold voltage of transistors. The conditions for the selection of parameters were found that ensure the same distribution of free carriers in thin-film structures for the cases of different thicknesses of films and the surrounding dielectrics. It was shown that the proposed approach can be used for a comparative analysis of the mobility in thin films and makes it possible to eliminate errors associated with different distributions of carriers in the films due to the coupling effect.

A 90-GHz Asymmetrical Single-Pole Double-Throw Switch With &gt;19.5-dBm 1-dB Compression Point in Transmission Mode Using 55-nm Bulk CMOS Technology

The millimeter-wave (mm-wave) single-pole double-throw (SPDT) switch designed in bulk CMOS technology has limited power-handling capability in terms of 1-dB compression point (P1dB) inherently. This is mainly due to the low threshold voltage of the switching transistors used for shunt-connected configuration. To solve this issue, an innovative approach is presented in this work, which utilizes a unique passive ring structure. It allows a relatively strong RF signal passing through the TX branch, while the switching transistors are turned on. Thus, the fundamental limitation for P1dB due to reduced threshold voltage is overcome. To prove the presented approach is feasible in practice, a 90-GHz asymmetrical SPDT switch is designed in a standard 55-nm bulk CMOS technology. The design has achieved an insertion loss of 3.2 dB and 3.6 dB in TX and RX mode, respectively. Moreover, more than 20 dB isolation is obtained in both modes. Because of using the proposed passive ring structure, a remarkable P1dB is achieved. No gain compression is observed at all, while a 19.5 dBm input power is injected into the TX branch of the designed SPDT switch. The die area of this design is only 0.26 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

The role of polarization in the threshold voltage of field effect transistors based on ZnO/MgO

In this work, we report on fabrication and characterization of a field effect transistor (FET) based on a ZnO/MgO bilayer employing a top-gate configuration. X-ray diffraction patterns show that the resulting ZnO and MgO films grow epitaxially with planes (002) and (111) parallel to the substrate surface, respectively. Typical current–voltage curves for different applied gate voltages are obtained, and the results are well fitted using standard FET equations. From these fittings, an extracted electronic mobility of μ = 0.8 cm2/V s was obtained in close agreement with the value extracted from Hall effect measurements. A threshold voltage of VTH=−34±3 V was obtained, which is the value that can be explained by the polarization difference of both materials. UV illumination shifts the VTH to VTH=−43±1 V. These findings show how the intrinsic properties of transparent conducting oxides can determine key parameters of a FET device.

Measurement and Evaluation of the Within-Wafer TID Response Variability on BOX Layer of SOI Technology

Within-wafer total ionizing dose (TID) response variability on buried oxide (BOX) layer of silicon-on-insulator (SOI) technology is investigated in this article. TID response variability is measured by the threshold voltage and OFF-state leakage of transistors evenly distributed on the wafer locations. Experimental results show the larger standard deviation of threshold voltage and OFF-state leakage distribution for irradiated devices than unirradiated devices, illustrating the within-wafer TID response variability. The hole traps variation in the BOX layer is responsible for the within-wafer TID response variability of SOI technology. Moreover, a data analysis method according to T-distribution is proposed to obtain the within-wafer TID response variability by the sampling testing results of limited wafer locations. Our data show that the T-distribution method is reasonable to assess the TID-induced variability of a process when only a few samples are available.

A high-sensitivity, low-noise dual-band RF energy harvesting and managing system for wireless bio-potential acquisition

This paper proposes a high-sensitivity, low-noise dual-band RF energy harvesting and managing system for wireless bio-potential acquisition. The proposed system consists of a dual-band RF energy harvester, a voltage monitor, and a power management unit (PMU). The proposed dual-band RF energy harvester adopts the hybrid threshold voltage self-compensation technology, which effectively reduces the equivalent threshold voltage of transistors and improves the power conversion efficiency (PCE). To match the input power and the load power with the minimum current consumption, a low-power voltage monitor is proposed in this paper. Moreover, the proposed PMU combines a voltage bootstrap circuit and a low-noise high-PSRR LDO to avoid the use of off-chip inductors and suppress output ripple. The proposed chip was implemented in a 0.18-μm deep n-well CMOS process, occupying a core area of 1.30 mm✕2.06 mm. The measured results show the dual-band RF energy harvester outputs a DC voltage of 1 V in two different frequency bands at the input power as low as −18.5 dBm. The PMU outputs stable DC voltages of 1 V and 1.8 V in working mode. In sleep mode, only the voltage monitor is working, and the average quiescent current is only 0.6 μA.

Effect of Electrode Materials on the Electrical Characteristics of Amorphous Indium-Tin-Gallium-Zinc Oxide Thin-Film Transistors.

In this study, we investigated the effect of electrode materials on the electrical characteristics of coplanar top-gate a-ITGZO thin-film transistors, in which the gate, source, and drain electrodes were made of the same metal, Ti or Al. The field-effect mobilities of the a-ITGZO thin-film transistors with Ti and Al electrodes were 35.2 and 20.1 cm²/V·s, respectively, and the threshold voltage of the a-ITGZO thin-film transistor with Ti electrodes was -0.4 V, whereas that of the transistor with Al electrodes was -1.8; this shift is attributed to the fact that Ti has a higher work function than Al. When Ti was used as the source and drain electrode material, the channel resistance and effective channel length were reduced owing to the penetration of metal atoms into the channel region from the edge of the source/drain electrodes.

An Approach for Drain Current Modeling Including Quantum Mechanical Effects for a DMDG Junctionless Field Effect Nanowire Transistor

This paper presents the effects of quantum confinements on the surface potential, threshold voltage, drain current, transconductance, and drain conductance of a Dual Material Double Gate Junctionless Field Effect Nanowire Transistor (DMDG-JLFENT). The carrier energy quantization on the threshold voltage of a DMDG-JLFENT is modeled, and subsequently, other parameters like drain current were analytically presented. The QME considered here is obtained under the quantum confinement condition for an ultra-thin channel, i.e., below 10 nm of Si thickness. The threshold voltage shift due to QME can be used as a quantum correction term for compact modeling of junctionless transistors. The analytical model proposed for surface potential, threshold voltage, drain current, transconductance, and drain conductance were verified by TCAD 3-D quantum simulation results which makes it suitable for SPICE compact modeling.

Maximized Hole Trapping in a Polystyrene Transistor Dielectric from a Highly Branched Iminobis(aminoarene) Side Chain.

We synthesized highly branched and electron-donating side chain subunits and attached them to polystyrene (PS) used as a dielectric layer in a pentacene field-effect transistor. The influence of these groups on dielectric function, charge retention, and threshold voltage shifts (ΔVth) depending on their positions in dielectric multilayers was determined. We compared the observations made on an N-perphenylated iminobisaniline side chain with those from the same side chains modified with ZnO nanoparticles and with an adduct formed from tetracyanoethylene (TCNE). We also synthesized an analogue in which six methoxy groups are present instead of two amine nitrogens. At 6 mol % side chain, hopping transport was sufficient to cause shorting of the gate, while at 2 mol %, charge trapping was observable as transistor threshold voltage shifts (ΔVth). We created three types of devices: with the substituted PS layer as single-layer dielectric, on top of a cross-linked PS layer but in contact with the pentacene (bilayers), and sandwiched between two PS layers in trilayers. Especially large bias stress effects and ΔVth, larger than those in the case of the hexamethoxy and previously studied dimethoxy analogues, were observed in the second case, and the effects increased with the increasing electron-donating properties of the modified side chains. The highest ΔVth was consistent with a majority of the side chains stabilizing the trapped charge. Trilayer devices showed decreased charge storage capability compared to previous work in which we used less donating side chains but in higher concentrations. The ZnO and TCNE modifications resulted in slightly more and less negative ΔVth, respectively, when the side chain polystyrene was not in contact with the pentacene and isolated from the gate electrode. The results indicate a likely maximum combination of molecular charge stabilizing activity and side chain concentration that still allows gate dielectric function.

Starter for Voltage Boost Converter to Harvest Thermoelectric Energy for Body-Worn Sensors

This paper examines the suitability of selected configurations of ultra-low voltage (ULV) oscillators as starters for a voltage boost converter to harvest energy from a thermoelectric generator (TEG). Important properties of particularly promising configurations, suitable for on-chip implementation are compared. On this basis, an improved oscillator with a low startup voltage and a high output voltage swing is proposed. The applicability of n-channel native MOS transistors with negative or near-zero threshold voltage in ULV oscillators is analyzed. The results demonstrate that a near-zero threshold voltage transistor operating in the weak inversion region is most advantageous for the considered application. The obtained results were used as a reference for design of a boost converter starter intended for integration in 180-nm CMOS X-FAB technology. In the selected technology, the most suitable transistor available with a negative threshold voltage was used. Despite using a transistor with a negative threshold voltage, a low startup voltage of 29 mV, a power consumption of 70 µW, and power conversion efficiency of about 1.5% were achieved. A great advantage of the proposed starter is that it eliminates a multistage charge pump necessary to obtain a voltage of sufficient value to supply the boost converter control circuit.

Physics-Based TCAD Simulation and Calibration of 600 V GaN/AlGaN/GaN Device Characteristics and Analysis of Interface Traps.

This study proposes an analysis of the physics-based TCAD (Technology Computer-Aided Design) simulation procedure for GaN/AlGaN/GaN HEMT (High Electron Mobility Transistor) device structures grown on Si (111) substrate which is calibrated against measurement data. The presence of traps and activation energies in the device structure will impact the performance of a device, the source of traps and position of traps in the device remains as a complex exercise until today. The key parameters for the precise tuning of threshold voltage (Vth) in GaN transistors are the control of the positive fixed charges −5 × 1012 cm−2, donor-like traps −3 × 1013 cm−2 at the nitride/GaN interfaces, the energy of the donor-like traps 1.42 eV below the conduction band and the acceptor traps activation energy in the AlGaN layer and buffer regions with 0.59 eV below the conduction band. Hence in this paper, the sensitivity of the trap mechanisms in GaN/AlGaN/GaN HEMT transistors, understanding the absolute vertical electric field distribution, electron density and the physical characteristics of the device has been investigated and the results are in good agreement with GaN experimental data.

Design of leakage current sensing technique based continues NBTI monitoring sensor using only NMOS

As the technology is scaled-down and with a decrease in oxide thickness, the effect of NBTI is a major reliability issue in semiconductor industries. NBTI is an aging phenomenon in which the PMOS transistor degraded over time. Deviation in the threshold voltage of PMOS transistor results from NBTI with stress time which affects various parameter of SRAM memory such as degradation in drain current, RSNM, HSNM and access time. NBTI induced aging effect on 6 T and 8 T SRAM cell have been analyzed in this paper for the stress time of 10 years. The reliability parameters of 6 T SRAM cell obtained from simulation result shows there is 6.53%, 23.86%, 3.36% and 13.42% change in Hold SNM (HSNM), Read SNM (RSNM), Write margin and standby leakage current respectively after 10 years. Similarly in 8 T SRAM cell HSNM, RSNM, Write margin and leakage current changes by 5.81%, 5.01%, 3.11%, and 13.24% respectively. This paper also presents the leakage current sensing technique based NBTI monitoring sensor using NMOS transistors only. The sensitivity of the sensor is 40 µV/nA and the linearity of the sensor is upto the practical leakage current range of SRAM cell. Thus we can conclude that the proposed sensor works fine with greater linearity and sensitivity.

A comparative study of integrated RF to DC power conversion system for RF energy harvesting

Battery power has been a popular choice of delivering DC power to many portable RF systems including wireless sensor nodes/internet of Everything (IoE). An autonomously powered RF system of the orders of 100’s of µwatts is becoming increasingly popular in recent times because of integrated solutions in energy harvesting. The minimum sensitivity of an RF energy harvester and the targeted deliverable output voltage for a specific load resistance are dictated by threshold voltage of transistors used and reverse leakage of such transistors. A detailed look into the architectures of rectifiers can help tackle design problems in the RF-DC conversion process. So in this work we focused on the design of integrated RF energy harvesting by studying four important architectures of RF-DC converters. To achieve a fair comparison between these architectures, a matching network operating at 0.8 MHz is designed and applied for simulation. All of these converters are tested in LT-SPICE XVII using the same designed matching network and the rectifiers are implemented in 180 nm CMOS technology.

Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Single Event Transient (SET) immunity. This novel D-latch can tolerate particles as charge injection in different internal nodes, as well as the input and output nodes. The performance of the new circuit has been assessed through different key parameters, such as power consumption, delay, Power-Delay Product (PDP) at various frequencies, voltage, temperature, and process variations. A set of simulations has been set up to benchmark the new proposed D-latch in comparison to previous D-latches, such as the Static D-latch, TPDICE-based D-latch, LSEH-1 and DICE D-latches. A comparison between these simulations proves that the proposed D-latch not only has a better immunity, but also features lower power consumption, delay, PDP, and area footprint. Moreover, the impact of temperature and process variations, such as aspect ratio (W/L) and threshold voltage transistor variability, on the proposed D-latch with regard to previous D-latches is investigated. Specifically, the delay and PDP of the proposed D-latch improves by 60.3% and 3.67%, respectively, when compared to the reference Static D-latch. Furthermore, the standard deviation of the threshold voltage transistor variability impact on the delay improved by 3.2%, while its impact on the power consumption improves by 9.1%. Finally, it is shown that the standard deviation of the (W/L) transistor variability on the power consumption is improved by 56.2%.

Low Power PPN inverter based 10T SRAM Cell

Objectives: In the present power-hungry world, the objective of this paper is to design a system that helps in the reduction of power consumption of systems. A memory cell, more specifically an SRAM cell being the major contributor to the increased power becomes an important unit to be considered in such systems for reducing power. This paper presents an improved single-ended PPN inverter based 10T SRAM cell. Methods: The proposed cell makes use of PPN-inverters. The CMOS inverter is replaced by the PPN-inverter in the conventional 8T SRAM cell giving an improved single-ended PPN-based 10T SRAM cell. Findings: The proposed work is compared with other SRAM cells based on delay, power dissipation, and power delay product (PDP). The proposed cell is designed and simulated on Cadence Virtuoso EDA tool version IC6.1.7 at a standard CMOS 45nm technology. The simulation results show that the proposed SRAM cell consumes lesser power and hence lower PDP compared to conventional 8T SRAM cell as well as other SRAM cells and with the use of high threshold voltage transistors in the read circuit a further decrease in the power consumption is observed. So, by use of PPN inverter in 8T SRAM cell a new design for low power consuming SRAM cell is achieved. Novelty: The proposed cell is optimized in terms of power dissipation making it more efficient for use in portable battery-operated devices. Keywords 10T SRAM cell, Low power, PPN inverter, Static Random­Access Memory (SRAM)

Degraded power MOSFET effects on Class-A power amplifier: Modelling studies considering feedback

The purpose of the study is proposing a gate oxide degraded MOSFET model that represents the degraded MOSFET effects on Class-A power amplifier parameters. The model includes electrical stress induced threshold voltage and transconductance parameter instabilities of transistor. The change in threshold voltage is between 3.2 V and -1 V; the change in transconductance parameter is between 0.4A/V2 and 0.004A/V2. The circuit model is formed by using a voltage source at the gate terminal and a resistor at the source terminal of transistor. Simulations with the proposed model are performed and simulation results are compared experimental DC and AC measurements of Class-A amplifier with and without feedback resistor during stress. To improve the model, we also proposed a tuning circuit. Its seen that, the proposed model in the study is successful to simulate the stress induced change in gain, efficiency of Class-A power amplifier.

A Multiple-Trapping-and-Release Transport Based Threshold Voltage Model for Oxide Thin Film Transistors

This article proposes a generic approach for modelling threshold voltage of oxide thin film transistors (TFTs). Threshold voltage has always been ambiguous in TFTs due to the disordered nature of semiconducting thin films, and in operation in accumulation mode. This differs from the situation with metal oxide field-effect transistors (MOSFETs), wherein strong inversion can be specifically defined. The proposed model considers double exponential distribution of deep state and tail state densities in the bandgap with the multiple-trapping-and-release (MTR) transport model. In this surface potential-based approach, pinned surface potential is defined as the surface potential at which free carrier densities exceed deep state carrier density in the deep state-dominated region. The threshold voltage is defined using pinned surface potential and carrier densities obtained at that surface potential. The model is validated using data from fabricated oxide based TFTs with silicon dioxide (SiO2) and other dielectrics. This article develops and reports a systematic approach for fitting an oxide based TFT analytical model with experimental devices, thus ensuring the flexibility needed for compatibility with various devices.