Ultra-Low-Voltage UTBB-SOI-Based, Pseudo-Static Storage Circuits for Cryogenic CMOS Applications

S S Teja Nibhanupudi,Jaydeep P Kulkarni,Siddhartha Raman Sundara Raman,Mikael Casse,Louis Hutin

doi:10.1109/jxcdc.2021.3130839

Abstract

Operating CMOS circuits at cryogenic temperatures offers advantages of higher mobility, higher ON-current, and better subthreshold characteristics, which can be leveraged to realize high-performance CMOS circuits. However, an ultra-low-voltage operation is necessary to minimize the power consumption and to offset the cooling cost overheads. The MOSFET threshold voltages (Vt) increase at cryogenic temperatures making it challenging to achieve high performance while operating at very low voltage. Ultra-thin body and buried oxide silicon-on-insulator (UTBB-SOI)-based MOSFETs can modulate the transistor threshold voltage using the back-gate bias, unlike conventional FinFETs. This unique UTBB-SOI technology attribute has been leveraged to realize compact pseudo-static storage circuits, namely, embedded dynamic random access memory (DRAM) bitcell and a flip-flop operating at 0.2 V and 77 K. This article presents UTBB-SOI device fabrication details and calibrate experimental device characteristics with BSIM compact models. SPICE simulations suggest the feasibility of three-transistor gain-cell embedded DRAM (eDRAM) capable of reliably storing three distinct voltage levels (1.5 bits/cell) and exhibiting retention time of the order of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s. Furthermore, a unique pseudo-static flip-flop design is presented, which can lower the clock power by 50%, transistor count by 20%, and static power consumption by 20%.

Highlights

T HE rapid growth in data-intensive applications has accelerated the need for computing systems having high-density energy-efficient memory combined with highperformance computing capability
We evaluate the performance of a 3T gain-cell embedded DRAM (eDRAM) for storing three distinct voltage levels in a single gain cell, achieving 1.5-bits/cell functionality
We present a pseudo-static flip-flop design that leverages the intrinsic gate capacitance of an inverter as a flip-flop storage element

Summary

INTRODUCTION

T HE rapid growth in data-intensive applications has accelerated the need for computing systems having high-density energy-efficient memory combined with highperformance computing capability. This work leverages the ease of threshold voltage tuning in UTBB-SOI technology using available work-function metals to demonstrate high-performance transistors operating at ultra-low voltage experimentally. Extreme low leakage currents in UTBB-SOI transistors are leveraged to realize compact pseudo-static storage circuits having higher storage density and lower power consumption. MULTILEVEL PSEUDO-STATIC MEMORY BITCELL The UTBB-SOI transistors operating at 77 K have a steep subthreshold slope (∼25 mV/dec), significantly reducing the drain-to-source leakage current. We evaluate the performance of multilevel, pseudo-static eDRAM bitcell designed using UTBB-SOI transistors operating at an ultra-low-voltage and cryogenic temperature conditions. The charge stored on the gate electrode of the read-port transistor (M2) is depleted gradually by the extremely low leakage current of M1 and M2 transistors This allows storing multiple voltage levels on the bitcell storage capacitance. This difference in the bitline voltage is resolved by a sense amplifier to determine the state stored in the bitcell

BITCELL PERFORMANCE

Findings

CONCLUSION