Threshold Voltage Of MOSFET Research Articles

Cryogenic threshold voltage and on-current variability comparative analysis of same-fab 65nm bulk and FDSOI MOSFETs

Cryogenic threshold voltage and on-current variability comparative analysis of same-fab 65nm bulk and FDSOI MOSFETs

Dynamic Bias-Temperature Instability Testing in SiC MOSFETs

For power converter development in mission critical applications, the attractive performances of SiC power MOSFETs are shadowed by reliability concerns, particularly those induced by the defects at the gate dielectric. Charge trapping at the oxide-semiconductor interface can lead to threshold voltage drift, degrading the power converter efficiency and lifetime. The scope of this contribution is to show a testing methodology under development to understand SiC power MOSFET threshold voltage stability under dynamic and accelerated operating conditions. The presented testing methodology relies on switching the device under test at high-voltage and current, simultaneously applying a gate stress and extracting threshold voltage from switching transients. The paper outlines the setup description, its operating modes and intended design of experiment to assess SiC MOSFET threshold voltage stability.

4H-SiC MOSFET Threshold Voltage Instability Evaluated via Pulsed High-Temperature Reverse Bias and Negative Gate Bias Stresses.

This paper presents a reliability study of a conventional 650 V SiC planar MOSFET subjected to pulsed HTRB (High-Temperature Reverse Bias) stress and negative HTGB (High-Temperature Gate Bias) stress defined by a TCAD static simulation showing the electric field distribution across the SiC/SiO2 interface. The instability of several electrical parameters was monitored and their drift analyses were investigated. Moreover, the shift of the onset of the Fowler-Nordheim gate injection current under stress conditions provided a reliable method to quantify the trapped charge inside the gate oxide bulk, and it allowed us to determine the real stress conditions. Moreover, it has been demonstrated from the cross-correlation, the TCAD simulation, and the experimental ΔVth and ΔVFN variation that HTGB stress is more severe compared to HTRB. In fact, HTGB showed a 15% variation in both ΔVth and ΔVFN, while HTRB showed only a 4% variation in both ΔVth and ΔVFN. The physical explanation was attributed to the accelerated degradation of the gate insulator in proximity to the source region under HTGB configuration.

Design of Lossless Negative Capacitance Multiplier Employing a Single Active Element

In this paper, a new negative lossless grounded capacitance multiplier (GCM) circuit based on a Current Feedback Operational Amplifier (CFOA) is presented. The proposed circuit includes a single CFOA, four resistors, and a grounded capacitor. In order to reduce the power consumption, the internal structure of the CFOA is realized with dynamic threshold-voltage MOSFET (DTMOS) transistors. The effects of parasitic components on the operating frequency range of the proposed circuit are investigated. The simulation results were obtained with the SPICE program using 0.13 µm IBM CMOS technology parameters. The total power consumption of the circuit was 1.6 mW. The functionality of the circuit is provided by the capacitance cancellation circuit. PVT (Process, Voltage, Temperature) analyses were performed to verify the robustness of the proposed circuit. An experimental study is provided to verify the operability of the proposed negative lossless GCM using commercially available integrated circuits (ICs).

Research on heavy ion irradiation effects on SOI SRAM

SRAM based on SOI devices has been widely used in aerospace storage devices due to its good electrical characteristics and radiation resistance. However, with the development of semiconductor technology, the feature size of devices continues to shrink, and the irradiation effects of high-energy ions have become increasingly serious. Single event effect has become the biggest threat to the failure of the spacecraft. A mixed-simulation method was used to research the heavy ion irradiation effects on SOI SRAM. SRAM consists of two coupled inverters. Firstly, the voltage changes of the inverter and SRAM output nodes under heavy ion irradiation were compared and analyzed, then the influence of the device itself and heavy ion parameters on the single particle flipping effect of the SRAM is investigated, and finally the necessary conditions for the flipping of the stored information in the SRAM are discussed and derived. The results show that heavy ion incidence does not permanently change the final state of the inverter; devices in the off state in the SRAM will undergo information flipping only when they are irradiated by heavy ions, and the threshold voltage of the N-type MOSFET is lower than that of the P-type MOSFET; an increase in the penetration depth will accelerate the flipping speed of the SRAM, but when the LET is high, the influence of the penetration depth on the flipping speed decreases; the change of the stored information in the SRAM is the result of the combined effect of pulse width and pulse height.

A MOSFET subdivision, MOSFET-only subthreshold voltage and current reference for LDO applications

This paper proposes a MOSFET-only voltage and current reference circuit, which can simultaneously provide a 2 V reference voltage and 300 nA reference current. This design is mainly used in a low-power Low-Dropout Regulator (LDO) project, after simulation verification, which works well in LDO applications. The circuit is performed by SMIC.18 CMOS technology and simulation with the Cadence platform, with different threshold voltage MOSFET circuit design. The whole circuit works in the subthreshold area, and the overall circuit consists of the start-up circuit, the current reference circuit, the voltage reference circuit, the MOSFET subdivision circuit, and the current mirror output circuit. The circuit has the characteristics of high precision and low power consumption, with a layout size of only 0.015 mm2. Under a temperature range of -30 to 70 °C and a power voltage of 3.3 V, the simulation and post-simulation temperature coefficients (TC) of the circuit are 5.4 ppm/°C and 19.4 ppm/°C, respectively. The post-simulation output reference voltage at room temperature is 2.0008 V, and the working power voltage within the circuit error range is 3.2 V to 3.4 V. Excluding the current mirror output circuit part of the Current-Quiescent (IQ) being 530 nA, the power consumption is 1.75 μW when the supply voltage is 3.3 V, and the design goal is reached.

Detailed comparison of threshold voltage extraction methods in FD-SOI MOSFETs

The threshold voltage in ultrathin FD-SOI MOSFETs is revisited from theoretical definitions to pragmatic extraction techniques, including novel ones. Their respective merits and limitations are underlined.

A New Low-Voltage Second Generation Voltage Conveyor Using Merged Voltage Follower and DTMOS Techniques

A very simple, compact and low-power second generation voltage conveyor circuit using only eight transistors is proposed in this work. Voltage follower stage is implemented using merged voltage follower (MVF), offering very low output impedance. A simple current mirror forms the input stage of the proposed voltage conveyor. To further enhance the linearity, another circuit is proposed where input transistor in MVF is replaced with DTMOS (Dynamic Threshold Voltage MOSFET), giving [Formula: see text][Formula: see text]mV linearity range as compared to [Formula: see text][Formula: see text]mV of the first proposal. Proposed-II VCII provides reduced offset voltage due to decreased effective threshold of DTMOS, and gain bandwidth product of the circuit also improves. Simulation results are computed using 180-nmCMOS technology with supply voltage of [Formula: see text][Formula: see text]V to validate the proposed circuits. Proposed-I and proposed-II VCII consume 85.1[Formula: see text][Formula: see text]W and 97.5[Formula: see text][Formula: see text]W, respectively. An application of the proposed conveyors as “current to voltage converter”, is also presented.

A Self-Powered DSSH Circuit with MOSFET Threshold Voltage Management for Piezoelectric Energy Harvesting.

This paper presents a piezoelectric (PE) energy harvesting circuit based on the DSSH (double synchronized switch harvesting) principle. The circuit consisted of a rectifier and a DC-DC circuit, which achieves double synchronized switch operation for the PE transducer in each vibration half-cycle. One of the main challenges of the DSSH scheme was precisely controlling the switch timing in the second loop of the resonant loops. The proposed circuit included a MOS transistor in the second loop to address this challenge. It utilized its threshold voltage to manage the stored energy in the intermediate capacitor per vibration half-cycle to simplify the controller for the DSSH circuit. The circuit can operate under either the DSSH scheme or the ESSH (enhanced synchronized switch harvesting) scheme, depending on the value of the intermediate capacitor. In the DSSH scheme, the following DC-DC circuit reused the rectifier's two diodes for a short period. The prototype circuit was implemented using 16 discrete components. The proposed circuit can be self-powered and started up without a battery. The experimental results showed that the proposed circuit increased the power harvested from the PE transducer compared to the full-bridge (FB) rectifier. With two different intermediate capacitors of 100 nF and 320 nF, the proposed circuit achieved power increases of 3.2 and 2.7 times, respectively. The charging efficiency of the proposed circuit was improved by a factor of 5.1 compared to the typical DSSH circuit.

Analytical models of the crosstalk voltage in SiC MOSFETs under different loads

AbstractDue to the higher switching speed and lower threshold voltage of SiC MOSFET, its crosstalk issue is more serious than that of Si devices. Firstly, the mechanism and process of crosstalk under resistive load and inductive load are compared and analyzed. Then, a parameter decoupling method based on energy conservation is proposed, and an analytical model of the crosstalk voltage under resistive load is established. Moreover, an analytical model of the crosstalk voltage under inductive load with only device and circuit parameters is introduced. Furthermore, the influence of the drive resistance and the common source inductance on the crosstalk voltage under different loads is evaluated through the analytical model. Finally, a double pulse test is carried out to verify the validity of the analysis. The results presented here can provide guidance for the design of gate circuit parameters to regulate the crosstalk issue of SiC MOSFETs under different loads.

Au Nanoparticles/HfO₂/Fully Depleted Silicon-on-Insulator MOSFET Enabled Rapid Detection of Zeptomole COVID-19 Gene With Electrostatic Enrichment Process

In this work, a novel sensing structure based on Au nanoparticles/HfO2/fully depleted silicon-on-insulator (AuNPs/HfO2/FDSOI) MOSFET is fabricated. Using such a planar double gate MOSFET, the electrostatic enrichment (ESE) process is proposed for the ultrasensitive and rapid detection of the coronavirus disease 2019 (COVID-19) ORF1ab gene. The back-gate (BG) bias can induce the required electric field that enables the ESE process in the testing liquid analyte with indirect contact with the top-Si layer. It is revealed that the ESE process can rapidly and effectively accumulate ORF1ab genes close to the HfO2 surface, which can significantly change the MOSFET threshold voltage ([Formula: see text]). The proposed MOSFET successfully demonstrates the detection of zeptomole (zM) COVID-19 ORF1ab gene with an ultralow detection limit down to 67 zM (~0.04 copy/[Formula: see text]) for a test time of less than 15 min even in a high ionic-strength solution. Besides, the quantitative dependence of [Formula: see text] variation on COVID-19 ORF1ab gene concentration from 200 zM to 100 femtomole is also revealed, which is further confirmed by TCAD simulation.

A MOS-DTMOS Implementation of Floating Memristor Emulator for High-Frequency Applications

The work presented in this article focuses on designing a floating MOS-dynamic threshold voltage MOSFET (DTMOS)-based circuit to emulate a memristor. The proposed circuit consists of four transistors, including a DT-MOSFET and an external capacitor, which helps obtain high-frequency operations up to 3 MHz. This facilitates easier integration of the devices and monolithic IC fabrication. The correctness of the proposed emulator is validated by conducting various parametric analyses at different operating frequencies and process corners, and it generates acceptable pinched hysteresis loops (PHLs) at various frequencies. Furthermore, pre- and post-layout validation of the proposed emulator are also performed using Cadence Virtuoso with Taiwan Semiconductor Manufacturing Company (TSMC) 180-nm process design kits (PDKs) to prove its effectiveness as a memristor. The area and power consumption of the proposed emulator are <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$157.48~\mu \text {m}^{2}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8.24~\mu \text {W}$ </tex-math></inline-formula> , respectively. The physical experiment of the proposed memristor emulator is performed using ALD <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1106~n$ </tex-math></inline-formula> -channel MOSFETs to characterize its functionality as a real-life memristor. It is also used in designing a memristor-based application to showcase its applicability in power and area optimal circuit design.

Proton induced radiation effect of SiC MOSFET under different bias

Radiation effects of silicon carbide metal–oxide–semiconductor field-effect transistors (SiC MOSFETs) induced by 20 MeV proton under drain bias (V D = 800 V, V G = 0 V), gate bias (V D = 0 V, V G = 10 V), turn-on bias (V D = 0.5 V, V G = 4 V) and static bias (V D = 0 V, V G = 0 V) are investigated. The drain current of SiC MOSFET under turn-on bias increases linearly with the increase of proton fluence during the proton irradiation. When the cumulative proton fluence reaches 2 × 1011 p⋅cm−2, the threshold voltage of SiC MOSFETs with four bias conditions shifts to the left, and the degradation of electrical characteristics of SiC MOSFETs with gate bias is the most serious. In the deep level transient spectrum test, it is found that the defect energy level of SiC MOSFET is mainly the ON2 (E c – 1.1 eV) defect center, and the defect concentration and defect capture cross section of SiC MOSFET with proton radiation under gate bias increase most. By comparing the degradation of SiC MOSFET under proton cumulative irradiation, equivalent 1 MeV neutron irradiation and gamma irradiation, and combining with the defect change of SiC MOSFET under gamma irradiation and the non-ionizing energy loss induced by equivalent 1 MeV neutron in SiC MOSFET, the degradation of SiC MOSFET induced by proton is mainly caused by ionizing radiation damage. The results of TCAD analysis show that the ionizing radiation damage of SiC MOSFET is affected by the intensity and direction of the electric field in the oxide layer and epitaxial layer.

The Influence of 10 MeV Proton Irradiation on Silicon Carbide Power Metal-Oxide-Semiconductor Field-Effect Transistor

The effects of 10 MeV proton irradiation on the threshold voltage and gate oxide reliability of SiC MOSFET are investigated. The negative shift of the threshold voltage was observed after irradiation, and the magnitude of the shift is exclusively related to the fluence and not the drain voltage. Moreover, proton irradiation leads up to the degeneration of oxide reliability. Experiment and simulation results indicate that the shift of the threshold voltage is caused by the total ionizing dose effect. Due to the superior blocking capabilities of the SiC MOSFET, the electric field of gate oxide is almost unaffected by the voltage applied to the drain, so the drift of threshold voltage is only related to particle fluence. The single event effect is responsible for the degradation of gate oxide reliability. The single event effect induces a transient high electric field in the gate oxide, which generates defects and affects the reliability of the gate oxide.

A four-quadrant analog multiplier using DTMOS for low power applications

ABSTRACT The four-quadrant analog multipliers (FQAM) are widely used in signal processing applications such as amplitude modulation, frequency doubling, and adaptive filters. In this paper, a FQAM has been realised in dynamic threshold voltage MOSFET (DTMOS) technology. It relies on the square-law characteristics of the MOS transistor. Several simulations have been carried out to assess the operation of the proposed FQAM. The supply voltage is set to ±0.2 V, and 68 µW power consumption is determined. The input signal can be applied to the full scale of the supply voltage. The bandwidth is 22.86 MHz, and the output signal’s total harmonic distortion (THD) is less than 2%. Intermodulation products of the output signal have been calculated. Monte Carlo and temperature simulations have been performed in a way that confirms the robustness of the circuit against the technological spread. In summary, low power consumption, wide bandwidth, and linearity are the advantages of the proposed circuit.

Case Study of Semiconducting Material

This electronic document is a “live” template and already There is no doubt that semiconductors changed the world beyond anything that could have been imagined before them. Although people have probably always needed to communicate and process data, it is thanks to the semiconductors that these two important tasks have become easy and take up infinitely less time than, e.g., at the time of vacuum tubes. Semiconductor materials are the building blocks of the entire electronics and computer industry. Small, lightweight, high speed, and low power consumption devices would not be possible without integrated circuits (chips), which consist of semiconductor materials. This paper provides a general discussion of semiconductor materials, their history, classification and the temperature effects in semiconductors. In this section we provide details about the impact of temperature on the MOSFET energy band gap, carrier density, mobility, carrier diffusion, velocity saturation, current density, threshold voltage, leakage current and interconnect resistance. We also provide the applications of semiconductor materials in different sectors of modern electronics and communications.

The influence of radiation on the electrical characteristics of MOSFET and its revival by different annealing techniques

Defects originate in N-channel MOSFETs by exposing them to high-energy ions and 60Co gamma radiation separately to different radiation doses. The electrical variations in MOSFETs are characterized systematically before and after the influence of radiation on MOSFETs. The impact of 60Co gamma radiation on threshold voltage (V TH) and mobility (µ) characteristics of MOSFETs is more than the impact of high energy ions on MOSFETs. The annealing of electrical characteristics in the irradiated MOSFETs is studied systematically by isothermal and isochronal annealing techniques. The isochronal annealing technique is more preferable due to its high recovery rate than the isothermal annealing technique.

Integrated Digital and Analog Circuit Blocks in a Scalable Silicon Carbide CMOS Technology

The wide bandgap of silicon carbide (SiC) has attracted a large interest over the past years in many research fields, such as power electronics, high operation temperature circuits, harsh environmental sensing, and more. To facilitate research on complex integrated SiC circuits, ensure reproducibility, and cut down cost, the availability of a low-voltage SiC technology for integrated circuits is of paramount importance. Here, we report on a scalable and open state-of-the-art SiC CMOS technology that addresses this need. An overview of technology parameters, including MOSFET threshold voltage, subthreshold slope, slope factor, and process transconductance, is reported. Conventional integrated digital and analog circuits, ranging from inverters to a 2-bit analog-to-digital converter, are reported. First yield predictions for both analog and digital circuits show great potential for increasing the amount of integrated devices in future applications.

Ultra-Low-Voltage UTBB-SOI-Based, Pseudo-Static Storage Circuits for Cryogenic CMOS Applications

Operating CMOS circuits at cryogenic temperatures offers advantages of higher mobility, higher ON-current, and better subthreshold characteristics, which can be leveraged to realize high-performance CMOS circuits. However, an ultra-low-voltage operation is necessary to minimize the power consumption and to offset the cooling cost overheads. The MOSFET threshold voltages (Vt) increase at cryogenic temperatures making it challenging to achieve high performance while operating at very low voltage. Ultra-thin body and buried oxide silicon-on-insulator (UTBB-SOI)-based MOSFETs can modulate the transistor threshold voltage using the back-gate bias, unlike conventional FinFETs. This unique UTBB-SOI technology attribute has been leveraged to realize compact pseudo-static storage circuits, namely, embedded dynamic random access memory (DRAM) bitcell and a flip-flop operating at 0.2 V and 77 K. This article presents UTBB-SOI device fabrication details and calibrate experimental device characteristics with BSIM compact models. SPICE simulations suggest the feasibility of three-transistor gain-cell embedded DRAM (eDRAM) capable of reliably storing three distinct voltage levels (1.5 bits/cell) and exhibiting retention time of the order of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s. Furthermore, a unique pseudo-static flip-flop design is presented, which can lower the clock power by 50%, transistor count by 20%, and static power consumption by 20%.

A Study on the Isolation Ability of LOCal Oxidation of SiC (LOCOSiC) for 4H-SiC CMOS Process

The oxidation rate of SiC can be greatly enhanced by pre-amorphization ion-implantation (PAI), and the PAI process has been employed to form the LOCal Oxidation of SiC (LOCOSiC) structure for device isolation in SiC integrated circuits (ICs). This work presents the study on the defect layer below the thermally grown SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and the impact of the defect layer on devices. The deep-level transient spectroscopy (DLTS) analysis reveals that the defect layer consists lots of C vacancies and Si vacancies. The leakage current of the edge-intensive N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /P-junction exhibits stronger temperature dependence than that of the P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /N-junction. This result confirms that C vacancy is an effective lifetime killer in n-type SiC, but not in p-type SiC. Although these defects increase the leakage current of the edge-intensive SiC N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /P-junction by 42 times at 150 °C compared with the junction with conventional chemical vapor deposited (CVD) field oxide (FOX), the leakage current is still much lower than the required OFF-state current of ICs. The defect layer has high resistance, and it is hard to let the SiC surface into inversion state so that the threshold voltage of the field MOSFET is higher than ±24 V.