Dynamic Bias-Temperature Instability Testing in SiC MOSFETs

Abstract

For power converter development in mission critical applications, the attractive performances of SiC power MOSFETs are shadowed by reliability concerns, particularly those induced by the defects at the gate dielectric. Charge trapping at the oxide-semiconductor interface can lead to threshold voltage drift, degrading the power converter efficiency and lifetime. The scope of this contribution is to show a testing methodology under development to understand SiC power MOSFET threshold voltage stability under dynamic and accelerated operating conditions. The presented testing methodology relies on switching the device under test at high-voltage and current, simultaneously applying a gate stress and extracting threshold voltage from switching transients. The paper outlines the setup description, its operating modes and intended design of experiment to assess SiC MOSFET threshold voltage stability.