Threshold Adaptive Memristor Research Articles

Efficient Training Method for Memristor-Based Array Using 1T1M Synapse

In this brief, an efficient training method for memristor-based array (crossbar) with one transistor and one memristor (1T1M) synapse is proposed, which enables parallel update of memristor-based arrays trained by stochastic gradient descent within two steps. Voltage ThrEshold Adaptive Memristor (VTEAM) model is utilized to describe memristor characteristics for simulations. On this basis, circuit parameters optimization method compensating the asymmetric and nonlinear weight update is provided for better training results. The effectiveness of proposed training method is evaluated on OR, AND functions and digit recognition task. Simulation results demonstrate the robustness of proposed training method to electrical noise and imperfections of memristors.

Performance degradation and I–V model of TiO2-film-based resistive switching memory under proton irradiation

The performance degradation of a TiO2-film-based RRAM (resistive random access memory) is investigated in a proton irradiation experiment with an energy of 25 MeV. The results reveal that the fabricated Au/TiO2 film/Ti devices exhibit typical I–V of bipolar resistive switching behavior under an irradiation of 1 × 1011 protons/cm2. The low-resistance state (LRS) resistance remains nearly constant, but the high-resistance state (HRS) resistance decreases with an increasing proton fluence. The value of the HRS resistance decreases by approximately one order of magnitude when the value of proton fluence reaches 1 × 1011 protons/cm2. Moreover, the SET voltage decreases with a decreasing proton fluence, while the RESET voltage remains almost constant. Material characterization via x-ray photoelectron spectroscopy demonstrates that the decrease in SET voltage and HRS resistance is mainly caused by radiation-induced oxygen vacancies and non-lattice oxygen. Based on the Voltage Threshold Adaptive Memristor model, a mathematical model of the I–V curve which demonstrates the variation in the RRAM resistance and voltage as a function of proton irradiation is constructed. The simulation results conformed to the experimental results under different proton fluences. Our results form a fundamental guide for the study of radiation performance degradation and radiation hardening of the RRAM with oxygen vacancy conducting filament.

A Unified Current-Voltage Model for Metal Oxide-Based Resistive Random-Access Memory.

Resistive random-access memory (RRAM) is essential for developing neuromorphic devices, and it is still a competitive candidate for future memory devices. In this paper, a unified model is proposed to describe the entire electrical characteristics of RRAM devices, which exhibit two different resistive switching phenomena. To enhance the performance of the model by reflecting the physical properties such as the length index of the undoped area during the switching operation, the Voltage ThrEshold Adaptive Memristor (VTEAM) model and the tungsten-based model are combined to represent two different resistive switching phenomena. The accuracy of the I-V relationship curve tails of the device is improved significantly by adjusting the ranges of unified internal state variables. Furthermore, the unified model describes a variety of electrical characteristics and yields continuous results by using the device's current-voltage relationship without dividing its fitting conditions. The unified model describes the optimized electrical characteristics that reflect the electrical behavior of the device.

An improved reconfigurable logic in resistive random access memory

Emerging non-volatile devices have shown great potential in computing in-memory (CIM). This work proposes a logic design method based on the complementary resistance switching (CRS) structure, which is connected by two anti-serially memristors. Three logics including AND, OR, and NIMP can be implemented in one step. Moreover, XOR logic can be implemented in two steps. Based on the proposed design, a 1-bit full adder is implemented with the fewer number of memristors and operation steps compared with existing works. The feasibility and correctness of our design are verified by the SPICE simulations with the Voltage Threshold Adaptive Memristor (VTEAM) model. In addition, we evaluate the ISCAS’85 benchmark circuit based on the proposed logic. Compared with existing methods, the performance and area overhead have been improved by the proposed method.

Convergence of a Class of Delayed Neural Networks with Real Memristor Devices

Neural networks with memristors are promising candidates to overcome the limitations of traditional von Neumann machines via the implementation of novel analog and parallel computation schemes based on the in-memory computing principle. Of special importance are neural networks with generic or extended memristor models that are suited to accurately describe real memristor devices. The manuscript considers a general class of delayed neural networks where the memristors obey the relevant and widely used generic memristor model, the voltage threshold adaptive memristor (VTEAM) model. Due to physical limitations, the memristor state variables evolve in a closed compact subset of the space; therefore, the network can be mathematically described by a special class of differential inclusions named differential variational inequalities (DVIs). By using the theory of DVI, and the Lyapunov approach, the paper proves some fundamental results on convergence of solutions toward equilibrium points, a dynamic property that is extremely useful in neural network applications to content addressable memories and signal-processing in real time. The conditions for convergence, which hold in the general nonsymmetric case and for any constant delay, are given in the form of a linear matrix inequality (LMI) and can be readily checked numerically. To the authors knowledge, the obtained results are the only ones available in the literature on the convergence of neural networks with real generic memristors.

A Memristor-Based High-Resolution A/D Converter

Based on the voltage threshold adaptive memristor (VTEAM) model, this paper proposes a circuit design of a memristor-based A/D converter, which can achieve high-resolution conversion by simple configuration. For this A/D converter, there are the input voltage stage and the reference voltage stage in one conversion. According to the memristance change in the two stages, the input analog voltage is converted as the corresponding digital value. In the input voltage stage, the memristance increases from the initial memristance. Meanwhile, the counter rises its value from zero to the maximum. Next, the memristance returns to the initial memristance in the reference voltage stage. At the same time, the counting value starts to increase from zero again. Then, the input analog voltage is mapped to the eventual counting value of the reference voltage stage. The simulations of the memristor-based A/D converter demonstrate that it has good conversion performance. The proposed memristor-based A/D converter not only has more brilliant performance than the CMOS A/D converter, but also has the advantages over existing memristor-based A/D converters of anti-interference ability and high resolution.

Uncorrelated stochastic bitstream generation and arithmetic computations using Cu:ZnO memristors

One popular approach under approximate computing is stochastic computing, wherein values are encoded in bitstreams to perform arithmetic operations in a low-power and computationally inexpensive manner. The stochastic computing paradigm, despite many advantages, is hindered by the need to generate uncorrelated input bitstream, which results in additional hardware overhead. In this work, Pt/Cu:ZnO/Nb:STO memristive devices were experimentally found to exhibit random switching behavior. The switching time was modeled as a Poisson distribution and the obtained results were utilized to develop a Stochastic Voltage Threshold Adaptive Memristor (SVTAM) model. Based on this circuit model, an innovative method to perform addition, multiplication and sum of product operations has been proposed by employing the memristor crossbar architecture. This implementation is advantageous as the row inputs can be reused across different columns of the crossbar to implement a large number of functions simultaneously in a compact arrangement. The functionality was verified using just 50 input pulses, and the error is just 1% when the number of pulses was increased to 200. In addition, the output is an uncorrelated bitstream, making it compatible with the existing stochastic computing circuits. This work presents a novel solution towards advancement in the field of approximate computing.

A radiation-hardened hybrid RRAM-based non-volatile latch

In this paper, a radiation-hardened resistive random-access memory (RRAM)-based non-volatile (NV) latch with a dual-interlocked storage cell is proposed and analyzed. The single-event effects of the proposed NV latch are simulated and discussed. Simulations of the proposed element are based on a 0.18 μm complementary metal-oxide-semiconductor design kit for the peripheral circuit and the voltage threshold adaptive memristor model for the RRAM. The simulation results indicate that the injected charge to induce a single-event upset (SEU) of the proposed NV latch is above 4.5 pC. As compared to the traditional RRAM based NV latch, the proposed NV latch is relatively immune to an SEU. This immunity from the SEU originates from the redundant storage nodes and interlocked feedback mechanism. Moreover, the area overhead of the proposed NV latch (eight transistors in the core storage element) are much lower than other radiation-hardened technology, e.g. TMR or FERST.

Memristor–CMOS hybrid ultra-low-power high-speed multivibrators

Memristor–CMOS (MCM) technology enables fabrication of thin film memristors over the conventional CMOS devices and has the potential to significantly reduce the silicon-area and propagation delays in VLSI chips. The memristor not only has an extremely very useful characteristic of non-volatile memory, but also has the advantage of significantly lesser ON resistance $$R_{on}$$ and lesser undesired parasitic capacitance as compared to MOSFETs. Innovative MCM hybrid re-configurable circuits can outperform conventional CMOS-only design and hence are being considered as an important device for future digital VLSI applications. This paper presents applications of $${\mathrm{TiO}}_{2-x}$$ – $${\mathrm{TiO}}_{2}$$ memristor for digital multivibrator circuits at 45 nm CMOS technology node. The threshold adaptive memristor SPICE model has been used for design and performance-benchmarking of the proposed MCM multivibrators in circuit simulator (cadence®) at 45 nm technology node. The proposed new MCM mono-stable vibrator has a delay of merely 16 ps (98% lower delay than similar CMOS design) and requires a 45% lesser silicon area. Similarly, the proposed new MCM bi-stable vibrator has a delay of merely 5 ps (87% lower delay than similar CMOS design) and requires a 25% lesser silicon area. Moreover, the proposed MCM mono-stable and bi-stable multivibrators consume merely 0.1 $$\upmu$$ W and 0.5 $$\upmu$$ W of power, respectively, as compared to the 0.47 $$\upmu$$ W and 0.98 $$\upmu$$ W power required by corresponding CMOS-only multi-vibrators. The overall decrease in power delay product is 99% and 94%, respectively, in the proposed MCM mono-stable and bi-stable multivibrators as compared to the corresponding conventional CMOS-only multivibrators.

Design of a Memristor-Based Digital to Analog Converter (DAC)

A memristor element has been highlighted in recent years and has been applied to several applications. In this work, a memristor-based digital to analog converter (DAC) was proposed due to the fact that a memristor has low area, low power, and a low threshold voltage. The proposed memristor DAC depends on the basic DAC cell, consisting of two memristors connected in opposite directions. This basic DAC cell was used to build and simulate both a 4 bit and an 8 bit DAC. Moreover, a sneak path issue was illustrated and its solution was provided. The proposed design reduced the area by 40%. The 8 bit memristor DAC has been designed and used in a successive approximation register analog to digital converter (SAR-ADC) instead of in a capacitor DAC (which would require a large area and consume more switching power). The SAR-ADC with a memristor-based DAC achieves a signal to noise and distortion ratio (SNDR) of 49.3 dB and a spurious free dynamic range (SFDR) of 61 dB with a power supply of 1.2 V and a consumption of 21 µW. The figure of merit (FoM) of the proposed SAR-ADC is 87.9 fj/Conv.-step. The proposed designs were simulated with optimized parameters using a voltage threshold adaptive memristor (VTEAM) model.

Modelling and Evolution of Conducting Filament in TiOx Memristor Using Conducting Atomic Force Microscopy.

Conducting filament evolution in TiOx based resistive switching memory fabricated by simple oxidation of Ti film is investigated. Formation of titanium oxide is confirmed from the X-ray diffraction study. Forming is required to initiate the switching process. A bipolar analog switching is observed with a positive set and negative reset voltage. The switching properties in TiOx layer owing to the formation of conducting filament is confirmed from the conducting atomic force micrograph at different bias voltage. A significant change in surface topography as a filament formation during set and reset is presented. Conduction mechanism inside the device at various voltage and effect of tunnel width on current is studied. The effective tunnel width of conduction filament and related parameters for device using device modelling (Threshold Adaptive Memristor model) is studied. The device can be used for synaptic applications.

(V)TEAM for SPICE Simulation of Memristive Devices With Improved Numerical Performance

The paper introduces a set of models of memristive devices for a reliable, accurate and fast analysis of large networks in the SPICE (Simulation Program with Integrated Circuit Emphasis) environment. The modeling starts from the recently introduced TEAM (ThrEshold Adaptive Memristor Model) and VTEAM (Voltage ThrEshold Adaptive Memristor Model). A number of improvements are made towards the stick effect elimination and other numerical refinements to make the analysis of large networks fast and accurate. A set of models are proposed that utilize the synergy of several techniques such as window asymmetrization, integration with saturation, state equation preprocessing, scaling, and smoothing. The performance of models is tested in Cadence PSPICE 17.2 and particularly in HSPICE v2017, the latter on a large-scale CNN (Cellular Nonlinear Network) for detecting edges of binary images. The simulations manifest the usability of developed models for fast and reliable operation in networks containing more than one million nodes.

TiO2−x–TiO2 Memristor Applications for Programmable Analog VLSI Circuits at 45 nm CMOS Technology Node

Memristor-CMOS (MCM) technology combines CMOS processing with nano-scale memristors enabling a significant reduction in the silicon area as compared to CMOS-only counterparts. Moreover, the non-volatile memory characteristics of the memristor offers opportunity for new and innovative MCM hybrid VLSI circuits that can outperform conventional CMOS designs. MCM based hybrid, homogeneous re-configurable architectures have already gained immense popularity among digital VLSI designers. This paper explores application of $$TiO_{2-x}$$ – $$TiO_{2}$$ charge trap memristor for programmable analog VLSI applications. The threshold adaptive memristor SPICE model has been used to evaluate the performance of the memristor in electronic design automation tool in conjunction with 45 nm CMOS devices. A digitally controlled MCM analog buffer, MCM binary phase shift keying modulator and a variable gain MCM differential amplifier has been presented in this paper. The MCM analog buffer has 81% greater gain-bandwidth product than the corresponding CMOS-only buffer and has an attenuation of $$-32$$ dB when the control signal is low. A MCM differential amplifier is proposed whose gain can be varied in both directions by shifting the operating point of the memristor through control signals, proving the advantages of using MCM technology for automatic gain control and other programmable analog VLSI applications. A MCM BPSK modulator circuit is also proposed which occupies 37.2% lesser silicon area than the conventional CMOS-only BPSK modulators, thus illustrating the utility of memristor in analog switching circuits.

Memristor‐based 2D1M architecture: Solution to sneak paths in multilevel memory

AbstractThe memristor, the fourth fundamental elements have shown the potential to revolutionize the present storage, analog, and digital computational technologies. The ability to remember its previous state in the absence of any stimuli has made the memristor as a prime candidate for nonvolatile memory. However, the sneak path is one of the main problems hampering the implementation of memristor‐based crossbar memories. In this article, we introduce a new crossbar architecture that is capable of storing multibit per cell and eliminates the sneak paths without adding any complex circuitry. The approximate write delay of the proposed memory cell is 20 mS which is very close to the delay of the single bit cell. The proposed architecture was validated by storing four different logic states in each cell of the 4 × 4 memory. Hence, one memory cell of the proposed architecture replaces four cells of the single‐bit memory at the cost of one additional diode per cell. Therefore, the proposed scheme saves considerable area when compared with the conventional single‐bit memory array. The write/read operations are validated by a generic, accurate, and efficient “voltage threshold adaptive memristor” (VTEAM) model. The simulation results prove that the proposed circuitry can read the memory content even after 2000 cycles without any sneak paths problem.

Variation-tolerant, low-power, and high endurance read scheme for memristor memories

Reading the memristor memory cell without changing its resistance state is one of the potential problems to be addressed in the memristor-based memory design. This paper presents a novel read scheme that achieves a non-destructive read operation, consumes less power, provides high endurance and adapts itself based on the process variations. The proposed scheme uses built-in self-tuning circuitry to obtain the optimum amplitude and width of the refresh pulse required to completely retrieve the state of the memristor after the read cycle. As the scheme uses refresh pulse only when needed, the scheme saves nearly 50% of average power when compared with a conventional fixed pulse read method. The self-tuning circuits are validated by a generic, accurate, and efficient “voltage threshold adaptive memristor” model. The validation results prove that the proposed tuning circuitry achieves optimum refresh pulse size under various read disturbance faults.

A Novel Design for Memristor-Based Multiplexer Via NOT-Material Implication

This paper proposes a novel memristor-based multiplexer implemented by using NOT-material implication. The proposed design can be extended to arbitrary ${N}$ -bit inputs and the enable-port can be added to improve its structure. Furthermore, this structure can be applied in the cascade circuit and crossbar array. A novel peripheral read circuit is introduced to overcome the problem that it is difficult to read out the operation results stored in crossbar array with large scales. The feasibility and correctness of our design is verified by the HSPICE simulation results with voltage threshold adaptive memristor model.

Radiation effects on memristor-based non-volatile SRAM cells

Memristors are a promising candidate for non-volatile memory elements. In this paper, we performed a radiation study on different memristor-based topological Non-Volatile Static Random Access Memory (NVSRAM). A Voltage ThrEshold Adaptive Memristor (VTEAM) model is considered for simulation analysis related to this work. In this paper, four different topologies, namely 3-Transistor 2-Memristor (3T2M) SRAM cell, 2-Transmission Gate 1-Memristor (2TG1M) SRAM cell, 1-Transistor 1-Memristor (1T1M) SRAM cell, and 4-Transistor 2-Memristor (4T2M) SRAM cell are investigated. A double-exponential current pulse is induced during a read operation and perturbation is observed due to irradiation. The memory cell retains its original state after radiation dose is removed. 4T2M SRAM topology is more reliable because its highest threshold current value is $$100\,{\upmu }\hbox {A}$$ , whereas 1T1M SRAM topology is less reliable with the lowest threshold current value of 5 nA.

Electrical Nonlinearity Emulation Technique for Current-Controlled Memristive Devices

Emerging memristor technology is recently drawing widespread attention due to its potential for diverse applications. Due to the lack of real solid-state memristive devices, there have been many initiatives to develop memristor emulators to study their behavior and applications. One of the most widely used ideal memristor models developed by the HP Lab does not fit the anticipated nonlinear behaviors of a real memristor. In this paper, we propose the concept and the design of a practical memristor emulator, which can be used to mimic the behavior of the well-known current controlled memristor models like- Simmons tunneling barrier model and the ThrEshold adaptive memristor model . Our proposed emulator model mimics the behavior of the electrical nonlinearity of the fabricated memristor. Prior emulators can only emulate the linear electrical behavior. In addition to the mathematical modeling and analysis of the proposed emulator, we provide SPICE simulation and experimental results. Furthermore, the proposed emulator has been used to verify some applications like Wien Oscillators. Finally, a brief comparison with the previously published emulators is presented to highlight the advantages of the proposed design.

VTEAM: A General Model for Voltage-Controlled Memristors

Memristors are novel electrical devices used for a variety of applications, including memory, logic circuits, and neuromorphic systems. Memristive technologies are attractive due to their nonvolatility, scalability, and compatibility with CMOS. Numerous physical experiments have shown the existence of a threshold voltage in some physical memristors. Additionally, as shown in this brief, some applications require voltage-controlled memristors to operate properly. In this brief, a Voltage ThrEshold Adaptive Memristor (VTEAM) model is proposed to describe the behavior of voltage-controlled memristors. The VTEAM model extends the previously proposed ThrEshold Adaptive Memristor (TEAM) model, which describes current-controlled memristors. The VTEAM model has similar advantages as the TEAM model, i.e., it is simple, general, and flexible, and can characterize different voltage-controlled memristors. The VTEAM model is accurate (below 1.5% in terms of the relative root-mean-square error) and computationally efficient as compared with existing memristor models and experimental results describing different memristive technologies.

Small-world Hopfield neural networks with weight salience priority and memristor synapses for digit recognition

A novel systematic design of associative memory networks is addressed in this paper, by incorporating both the biological small-world effect and the recently acclaimed memristor into the conventional Hopfield neural network. More specifically, the original fully connected Hopfield network is diluted by considering the small-world effect, based on a preferential connection removal criteria, i.e., weight salience priority. The generated sparse network exhibits comparable performance in associative memory but with much less connections. Furthermore, a hardware implementation scheme of the small-world Hopfield network is proposed using the experimental threshold adaptive memristor (TEAM) synaptic-based circuits. Finally, performance of the proposed network is validated by illustrative examples of digit recognition.