An improved reconfigurable logic in resistive random access memory

Abstract

Emerging non-volatile devices have shown great potential in computing in-memory (CIM). This work proposes a logic design method based on the complementary resistance switching (CRS) structure, which is connected by two anti-serially memristors. Three logics including AND, OR, and NIMP can be implemented in one step. Moreover, XOR logic can be implemented in two steps. Based on the proposed design, a 1-bit full adder is implemented with the fewer number of memristors and operation steps compared with existing works. The feasibility and correctness of our design are verified by the SPICE simulations with the Voltage Threshold Adaptive Memristor (VTEAM) model. In addition, we evaluate the ISCAS’85 benchmark circuit based on the proposed logic. Compared with existing methods, the performance and area overhead have been improved by the proposed method.