Three-dimensional Integration Technology Research Articles

Low-temperature sinterability of graphene-Cu nanoparticles:Molecular dynamics simulations and experimental verification

As three-dimensional integration technology evolves, the integration density and operating speed of circuits continue to increase, raising the demands for interconnect reliability. It is urgent to explore novel interconnect materials to meet reliability requirements. Given its excellent mechanical, physical, and electrical properties, graphene-nanocopper has emerged as a promising new interconnect material. However, graphene’s low affinity with copper requires an exploration of its sintering mechanism to guide the sintering process. In this study, we initially utilized molecular dynamics calculations to compare the sintering processes of Cu NPs and G@Cu NPs. Graphene limits the sintering progress of G@Cu NPs, with shear strengths of Cu NPs (8.38 MPa) < G@Cu NPs (12.78 MPa) < benzimidazole@Cu NPs (13.28 MPa), and porosity rates of Cu NPs (38.19 %) > G@Cu NPs (14.28 %) > benzimidazole@Cu NPs (10.36 %). Post-sintering service reliability verifies that graphene limits the sintering process of G@Cu NPs. The sintering process of graphene with copper was subsequently simulated for different core–shell diameters, within a specific range, revealing that increasing the copper core diameter and graphene shell thickness decreases the sintering progression. However, the increase in graphene may concurrently alter defects, thus accelerating the sintering process. Finally, simulations conducted at sintering temperatures of 473 K, 573 K, and 673 K for G@Cu NPs show that increasing the temperature accelerates the sintering process, reducing the porosity rate from 19.48 % to 12.64 % and increasing the shear strength from 10.14 MPa to 13.92 MPa. It was verified that the temperature increase promoted the G@Cu sintering process. Our research reveals atomistic changes in G@Cu NPs under low-temperature conditions and provides a deeper understanding of low-temperature sintering for G@Cu NPs.

Nitrogen: A promising doping strategy for high-performance ovonic threshold switching selectors

The Ovonic Threshold Switching (OTS) selector serves as an essential component in the development of three-dimensional high-density memory integration technology. Nevertheless, the state-of-the-art high-performance OTS materials usually contain toxic elements such as arsenic (As), posing significant risks to both environmental and human health. Nitrogen (N), which belongs to the same group as arsenic (As), has emerged as a highly promising alternative for As doping. However, the underlying mechanisms that govern N-based OTS materials have not yet been extensively investigated. In this study, we delve into the effects of N doping on the structural, bonding, and electronic properties of amorphous GeSe (a-GeNSe) by ab initio molecular dynamics simulations to bridge the knowledge gap. Our findings indicate that upon N doping in a-GeSe, the formation of robust Ge-N bonds, along with N-centered tetrahedral and triangular structures, resulting in the sluggish atomic movement that enhances the thermal stability and endurance of a-GeNSe. The OTS characteristics are significantly influenced by the material’s electronic band structure, and thus the relatively slow performance drift can be attributed to the stabilization of mid-gap states, a result of N doping which effectively slows down the aging process of chalcogenide glass. Moreover, the increased mobility gap in a-GeNSe raises the threshold voltage (Vth), making it more compatible with commercially available phase-change memory materials. Our findings reveal the extensive impact of the N element on a typical OTS material and offer valuable perspectives for alternative doping strategies that could potentially supplant As practices.

Research of Vertical via Based on Silicon, Ceramic and Glass.

With the increasing demand for high-density integration, low power consumption and high bandwidth, creating more sophisticated interconnection technologies is becoming increasingly crucial. Three-dimensional (3D) integration technology is known as the fourth-generation packaging technology beyond Moore's Law because of its advantages of low energy consumption, lightweight and high performance. Through-silicon via (TSV) is considered to be at the core of 3D integration because of its excellent electrical performance, lower power consumption, wider bandwidth, higher density, smaller overall size and lighter weight. Therefore, the particular emphasis of this review is the process flow of TSV technology. Among them, the research status of TSV hole etching, deep hole electroplating filling and chemical mechanical planarization (CMP) in TSV preparation process are introduced in detail. There are a multitude of inevitable defects in the process of TSV processing; thus, the stress problems and electrical characteristics that affect the reliability of TSV are summarized in this review. In addition, the process flow and process optimization status of through ceramic via (TCV) and through glass via (TGV) are discussed.

A Compact Sixth-Order Common-Mode Noise Suppression Filter Based on 3-D Integration Technology

Based on three-dimensional (3-D) integration technology, a compact sixth-order common-mode noise suppression filter is proposed according to delay line theory. As the important parts of the filter, the on-chip inductors are established by through-silicon vias (TSVs) and the capacitors are realized by double layer interdigital structure. Compared with other relative literatures, the proposed filter has a minimized size of 0.29×0.32 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (0.0203 × 0.0224 λg <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ). And it can suppress the common-mode noise more than 10 dB from 3.8 to 8.6 GHz or more than 20 dB from 4.45 to 7.85 GHz. Meanwhile, the differential signal insertion loss is kept less than 3dB.

Probing molecular structures at buried solid/solid interfaces involving low-k materials or polymers in situ nondestructively: a review

BackgroundWith the development of three-dimensional (3D) integration technology including extreme ultraviolet (EUV) lithography, more and more buried interfaces are involved in a device. It is important to probe such buried solid/solid interfaces in situ, but due to the lack of appropriate metrology, it is difficult to do so.AimThis review aims to introduce sum frequency generation (SFG) vibrational spectroscopy to researchers and engineers in the research fields related to 3D integration technology including EUV lithography. SFG can probe buried solid/solid interfaces in situ nondestructively.Review ApproachThis review presents the SFG technique and the recent results obtained from SFG studies on a variety of solid/solid interfaces, including porous low-k material/silicon interfaces, plasma treated polymer/epoxy interfaces, flux treated metal/epoxy interfaces, chemical reactions at buried solid/solid interfaces, and structures of buried solid/solid interfaces in multilayered thick device.ConclusionsSFG has been successfully applied to elucidate molecular structures and molecular interactions at buried solid/solid interfaces in situ nondestructively. SFG has great potential to probe buried interfaces in devices based on 3D integration technology.

Microstructural and mechanical characteristics of Cu-Sn intermetallic compound interconnects formed by TLPB with Cu-Sn nanocomposite

Transient liquid phase bonding (TLPB) is a promising technology for three-dimensional integration of circuits (3D IC), but it can be slow and less productive. A novel Cu-Sn nanocomposite interlayer (Cu-Sn NI) composed of Sn matrix with an embedded Cu nanowire array prepared by electrodeposition can significantly accelerate the bonding process, approximately by 20 times. Bonding time with a Cu-Sn NI can be as short as ~2 min to achieve a full Cu-Sn intermetallic compound (IMC) joints, whereas it can take ~60 min with a pure Sn interlayer of the same thickness under the same bonding conditions (250 °C). Unlike the columnar Cu 6 Sn 5 grains commonly formed with Sn interlayer, refined equiaxed Cu 6 Sn 5 grains with an average size of ~1.6 µm are found to be formed with Cu-Sn NI. Such grain refinement has significantly contributed to the improvement of shear strength of IMC joints formed with Cu-Sn NI (23.1 ± 3.3 MPa), higher than those bonded with pure Sn interlayer (17.9 ± 2.1 MPa). The underlying mechanisms of the new TLPB process and the formation of finer microstructure when bonding with Cu-Sn NIs are also illuminated and validated based on the experimental observation. • A unique Cu-Sn nanocomposite interlayer with Cu nanowire array embedded in Sn. • TLPB with this layer is >20 times faster than conventional Cu-Sn TLPB. • IMC joint bonded with this layer possesses refined equiaxed Cu 6 Sn 5 grains. • Strength of IMC joint bonded with this layer is higher than pure Sn layer. • Clarified the growth mechanisms of IMC in the joints bonded with this layer.

A W-Band Active Phased Array Miniaturized Scan-SAR with High Resolution on Multi-Rotor UAVs

The smart unmanned aerial vehicle (UAV) with a mini-SAR payload provides an advanced earth observation capability for target detection and imaging. Simiar to large-scale SAR, mini-SAR also has an increasing requirement for high resolution and wide swath. However, due to the low cruising altitude of UAVs, small coverage angles in the direction range, and the insufficient operating range of mini-SAR, expanding the swath has become an urgent problem for mini-SAR. To solve this problem, this paper proposes a W-Band active phased array miniaturized SAR (APA mini-SAR), whose scanning capacity has been proven on the multi-rotor UAV platform. Many efforts, including the novel active phased array antenna scheme, the sparse triangular arrangement of antenna elements, the wideband chirp source, and the three-dimensional integration technology, have been made to develop this APA mini-SAR for the first time in the W-Band. The volume of this APA mini-SAR is 69 × 82 × 87 mm3, with a weight of 600 g. Combined with a new motion compensation strategy and the ω-k imaging algorithm, the focused image is finally obtained. Experiments have been conducted, and the results indicate that this APA mini-SAR has a resolution of 4.5 cm, the imaging swath is three times that of the traditional single-channel mini-SAR, and the operating range is increased to 800 m.

Software/Hardware Co-design of 3D NoC-based GPU Architectures for Accelerated Graph Computations

Manycore GPU architectures have become the mainstay for accelerating graph computations. One of the primary bottlenecks to performance of graph computations on manycore architectures is the data movement. Since most of the accesses in graph processing are due to vertex neighborhood lookups, locality in graph data structures plays a key role in dictating the degree of data movement. Vertex reordering is a widely used technique to improve data locality within graph data structures. However, these reordering schemes alone are not sufficient as they need to be complemented with efficient task allocation on manycore GPU architectures to reduce latency due to local cache misses. Consequently, in this article, we introduce a software/hardware co-design framework for accelerating graph computations. Our approach couples an architecture-aware vertex reordering with a priority-based task allocation technique. As the task allocation aims to reduce on-chip latency and associated energy, the choice of Network-on-Chip (NoC) as the communication backbone in the manycore platform is an important parameter. By leveraging emerging three-dimensional (3D) integration technology, we propose design of a small-world NoC (SWNoC)-enabled manycore GPU architecture, where the placement of the links connecting the streaming multiprocessors (SMs) and the memory controllers (MCs) follow a power-law distribution. The proposed 3D SWNoC-enabled software/hardware co-design framework achieves 11.1% to 22.9% performance improvement and 16.4% to 32.6% less energy consumption depending on the dataset and the graph application, when compared to the default order of dataset running on a conventional planar mesh architecture.

Photonic and optoelectronic neuromorphic computing

Recent advances in neuromorphic computing have established a computational framework that removes the processor-memory bottleneck evident in traditional von Neumann computing. Moreover, contemporary photonic circuits have addressed the limitations of electrical computational platforms to offer energy-efficient and parallel interconnects independently of the distance. When employed as synaptic interconnects with reconfigurable photonic elements, they can offer an analog platform capable of arbitrary linear matrix operations, including multiply–accumulate operation and convolution at extremely high speed and energy efficiency. Both all-optical and optoelectronic nonlinear transfer functions have been investigated for realizing neurons with photonic signals. A number of research efforts have reported orders of magnitude improvements estimated for computational throughput and energy efficiency. Compared to biological neural systems, achieving high scalability and density is challenging for such photonic neuromorphic systems. Recently developed tensor-train-decomposition methods and three-dimensional photonic integration technologies can potentially address both algorithmic and architectural scalability. This tutorial covers architectures, technologies, learning algorithms, and benchmarking for photonic and optoelectronic neuromorphic computers.

Enhancement of the Bond Strength and Reduction of Wafer Edge Voids in Hybrid Bonding.

The hybrid wafer bonding technique is drawing much interest in relation to three-dimensional integration technology, and its areas of application are expanding from image sensors to semiconductor memory packages. In hybrid bonding, the bond strength and void formation are the main issues influencing the performance, reliability, and yield of the bonding. In this study, we systematically investigate several parameters that affect both the bond strength and void formation, including the plasma gas, plasma power, and surface roughness. In particular, the effects of the wafer warpage on void formation were investigated. As O2 gas was used during plasma activation, the highest oxide growth rate and strongest bond strength were achieved. The bond strength improved when the oxide thickness was increased. An increase in the low-frequency plasma power improved the bond strength. However, when the plasma power increased further, the surface roughness increased due to the ion bombardment effect during the use of the plasma, resulting in a reduction in the bond strength. Therefore, optimization of the plasma power is required to improve the bond strength. It was found that the wafer warpage was also an important parameter which affected the formation of edge voids. The wafers with residual compressive stress exhibited fewer edge voids than those with tensile stress. Several methods to minimize edge void formation in wafers are proposed. The present study will provide practical guidelines to enhance the quality and yield of the bonding process and devices.

Wafer-Level 3D Integration Based on Poly (Diallyl Phthalate) Adhesive Bonding

Three-dimensional integration technology provides a promising total solution that can be used to achieve system-level integration with high function density and low cost. In this study, a wafer-level 3D integration technology using PDAP as an intermediate bonding polymer was applied effectively for integration with an SOI wafer and dummy a CMOS wafer. The influences of the procedure parameters on the adhesive bonding effects were determined by Si–Glass adhesive bonding tests. It was found that the bonding pressure, pre-curing conditions, spin coating conditions, and cleanliness have a significant influence on the bonding results. The optimal procedure parameters for PDAP adhesive bonding were obtained through analysis and comparison. The 3D integration tests were conducted according to these optimal parameters. In the tests, process optimization was focused on Si handle-layer etching, PDAP layer etching, and Au pillar electroplating. After that, the optimal process conditions for the 3D integration process were achieved. The 3D integration applications of the micro-bolometer array and the micro-bridge resistor array were presented. It was confirmed that 3D integration based on PDAP adhesive bonding is suitable for the fabrication of system-on-chip when using MEMS and IC integration and that it is especially useful for the fabrication of low-cost suspended-microstructure on-CMOS-chip systems.

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and solder bumping processes are the key interconnection technologies that satisfy the former requirements and receive the most attention from the electronic industries. This review mainly includes two directions to get a precise understanding, such as the TSV filling and solder bumping, and explores their reliability aspects. TSV filling addresses the DRIE (deep reactive ion etching) process, including the coating of functional layers on the TSV wall such as an insulating layer, adhesion layer, and seed layer, and TSV filling with molten solder. Solder bumping processes such as electroplating, solder ball bumping, paste printing, and solder injection on a Cu pillar are discussed. In the reliability part for TSV and solder bumping, the fabrication defects, internal stresses, intermetallic compounds, and shear strength are reviewed. These studies aimed to achieve a robust 3D integration technology effectively for future high-density electronics packaging.

Morphometry and displacement analysis of the upper lips following maxillary full-arch implant-supported fixed prostheses: a 3D morphometric study

BackgroundWith the emergence of three-dimensional (3D) integration technology, analysis of soft tissue displacement and morphological changes after maxillary full-arch implant-supported fixed prostheses can be performed. The aim of this study was to verify the feasibility of the 3D integration method for constructing the relative position of the prostheses and facial soft tissue, evaluate the displacement and morphological variation of the upper lips after maxillary full-arch implant-supported fixed prostheses.MethodsTwenty-five maxillary edentulous patients were recruited in this study. At the time of final prosthesis delivery, the 3D prostheses data and three 3D facial profiles were integrated. After method validation, the 3D position changes of seven soft tissue landmarks were used to reflect the 25 upper lips. The variation of four morphological distances were analyzed to reflect the morphological alteration of the upper lips. Two pairs of dentofacial landmarks were used to analyze the sagittal relative position of the prostheses and soft tissue. The included patients were also grouped to determine the impact of sex, upper lip thickness, and length on lip support changes.ResultsThe average distance of the two matched relative reliable forehead regions was only 0.32 mm. The sagittal shifts of labrale superius (LS), stomion (STO), crista philtri left (CPHL) and crista philtri right (CPHR) were 3.44 ± 1.39 mm, 2.52 ± 1.38 mm, 3.04 ± 1.18 mm, and 3.12 ± 1.21 mm, respectively. With the exception of the decrease in the length of subnasale (SN)-LS, the length of cheilion right (CHR)-cheilion left (CHL), CPHR-CPHL, and LS-STO significantly increased. The two pairs of dentofacial landmarks had strong positive movement correlations along the sagittal direction. Patients with thinner and longer lips showed more lip support than those with thicker and shorter lips by a clinically insignificant amount.ConclusionsThe integration method of 3D facial and dental data showed high repeatability in constructing the dentofacial relative position. The linear equations reflecting dentofacial relative position could aid clinicians in evaluating the restoration effect and estimate the upper lip variation.

High TEC Copper to Connect Copper Bond Pads for Low Temperature Wafer Bonding

Copper to copper wafer hybrid bonding is the most promising technology for three-dimensional (3D) integration. In the hybrid bonding process, two silicon wafers are aligned and contacted. At room temperature (RT), these aligned copper pads contain radial-shaped nanometer-sized hollows due to the dishing effect induced by chemical-mechanical polishing (CMP). These wafers are annealed for copper to expand and connect upper and lower pads. This copper expansion is key to eliminate the radial-shaped hollows and make copper pads contacted. Therefore, in this research, we investigated the new high thermal expansion coefficient (TEC) electrodeposited copper to eliminate the dishing hollows at lower temperature than that with conventional copper using the combination of new additive A and low TEC additives. The TEC of new electrodeposited copper is 25.2 × 10−6 °C−1, 46% higher than conventional copper and the calculated contact area of copper surface at 250 °C with 5 nm dishing depth is 100%.

A three-dimensional and multi-source integrated technology system for controlling rural non-point source pollution in the Three Gorges Reservoir Area, China

Techniques for controlling rural non-point source pollution (RNSP) represent cleaner production techniques that can provide an effective guarantee for regional sustainable development. The majority of studies on RNSP control technologies are mainly aimed at handling only a single pollution source. However, such studies are difficult to perform in rural areas, which have dense populations, complex terrains and extreme climates, such as the Three Gorges Reservoir Area (TGRA), China. Therefore, this paper focuses on the application of the RNSP control technologies based on the following four aspects: crop planting, livestock production, domestic inputs and water-level-fluctuating (WLF) zone. Based on the unique topography, land features and planting patterns of the TGRA, a three-dimensional (3D) and multi-source integrated technology system for controlling RNSP was established according to the principle of source reduction, runoff regulation, and nitrogen (N) and phosphorus (P) loss control. From the results of the long-term observations, the risk of RNSP has been significantly reduced in the study area. The nutrient capacity of the soil increased by 9–15%, while the chemical fertilizer application reduced by 30–50%. The loss of sediment, N and P were reduced by 60–80%, 30–70% and 50–90% in the sloping land at the backslope, respectively, by 30–60%, 70–90%, and 70–90% in the paddy field at the footslope, respectively, and by 75–90%, 30–50%, 65–95% in the WLF zone, respectively. The average removal rates of COD, NH3-N and TN in sewage in the residential area were higher than 82%, 87% and 63.3%, respectively. Overall, more than 90% of RNSP was reduced by using this 3D and multi-source technology system, and it can be widely promoted for controlling RNSP in similar ecological areas with support from local governments by implementing effective measures, such as strengthening environmental protection education and government subsidies.

Fully epitaxial giant magnetoresistive devices with half-metallic Heusler alloy fabricated on poly-crystalline electrode using three-dimensional integration technology

Fully-epitaxial magnetoresistance (MR) devices with half-metallic Heusler alloys has attracted considerable attention for years due to their excellent spin-dependent transport properties such as high MR ratio and ultra-low resistance-area product. However, their poor manufacturability due to the necessity of epitaxial growth on a special single crystalline substrate such as MgO(001) hinders their practical applications. To overcome this issue, in this study, we fabricated Heusler-based epitaxial current-perpendicular-to-plane giant magnetoresistance (CPP-GMR) film grown on Si substrate and directly bonded it to poly-crystalline electrode wafer by using three-dimensional (3D) integration processes such as direct wafer bonding and removal of backside Si substrate. First we explored suitable seed/buffer layers for the (001)-oriented epitaxial growth of Heusler CPP-GMR on Si(001) substrate. Si-subs/NiAl/CoFe seed/buffer structure was found to induce (001)-oriented epitaxial growth and to suppress an Al diffusion from NiAl to the Heusler electrode even after annealing at 500 °C, resulting in large MR ratio comparable to that with MgO substrate. After direct wafer bonding process, the microstructure analysis revealed clean damage-free bonded interface between the epitaxial Heusler GMR and poly-crystalline electrode films with Au capping layers. After the 3D integration processes, high MR performance has been successfully reproduced. This unique processing method enables the integration of high performance Heusler-based epitaxial spintronic devices for various practical applications.

Tutorial on forming through-silicon vias

Through-silicon vias (TSVs) are a critical technology for three-dimensional integrated circuit technology. These through-substrate interconnects allow electronic devices to be stacked vertically for a broad range of applications and performance improvements such as increased bandwidth, reduced signal delay, improved power management, and smaller form-factors. There are many interdependent processing steps involved in the successful integration of TSVs. This article provides a tutorial style review of the following semiconductor fabrication process steps that are commonly used in forming TSVs: deep etching of silicon to form the via, thin film deposition to provide insulation, barrier, and seed layers, electroplating of copper for the conductive metal, and wafer thinning to reveal the TSVs. Recent work in copper electrochemical deposition is highlighted, analyzing the effect of accelerator and suppressor additives in the electrolyte to enable void-free bottom-up filling from a conformally lined seed metal.

Development of a fast atom beam gun for surface-activated bonding

Surface-activated bonding (SAB), also called room-temperature bonding, is used in three-dimensional integration technology for semiconductor devices. An Ar fast atom beam (FAB) is used for SAB. However, conventional FAB guns must be replaced after hundreds of minutes of irradiation because carbon abrasion powders are generated by Ar ions sputtering in the gun. Therefore, this study develops a novel FAB gun with improved lifetime. The proposed FAB gun applies magnetic fields to guide Ar ions to reduce sputtering in the gun and improve irradiation efficiency. The proposed FAB gun indicates the possibility of improving gun lifetime.

Reconfigurable horizontal–vertical carrier transport in graphene/HfZrO field-effect transistors

We have fabricated at wafer level field-effect-transistors (FETs) having as channel graphene monolayers transferred on a HfZrO ferroelectric, grown by atomic layer deposition on a doped Si (100) substrate. These FETs display either horizontal or vertical carrier transport behavior, depending on the applied gate polarity. In one polarity, the FETs behave as a graphene FET where the transport is horizontal between two contacts (drain and grounded source) and is modulated by a back-gate. Changing the polarity, the transport is vertical between the drain and the back-gate and, irrespective of the metallic contact type, Ti/Au or Cr/Au, the source–drain bias modulates the height of the potential barrier between HfZrO and the doped Si substrate, the carrier transport being described by a Schottky mechanism at high gate voltages and by a space-charge limited mechanism at low gate voltages. Vertical transport is required by three-dimensional integration technologies to increase the density of transistors on chip.

Design of Phased Array T/R Component Microsystem Based on Heterogeneous Integration Technology

An X-band silicon-based 2×2 phased array T/R module was developed based on MEMS technology and three-dimensional heterogeneous integration technology such as through-silicon via (TSV). The module uses a transceiver integrated multifunction chip solution and is packaged in two layers of silicon: upper layer integrated low noise amplifier, power amplifier, switch, power modulation driver, PMOS and other chips; lower layer integrated multi-function chip, serial-to-parallel chip, logic operation chip. Two-layer silicon package are stacked by solder balls. The T/R module sample’s size is 20mm×20mm×3mm. The test results show that at 8-12GHz, the transmit power is higher than 29dBm, the transmit gain is 20dB, the receive gain is 29dB, the noise figure (NF) is 3dB, and the switch isolation is 37dB.