Abstract
Through-silicon vias (TSVs) are a critical technology for three-dimensional integrated circuit technology. These through-substrate interconnects allow electronic devices to be stacked vertically for a broad range of applications and performance improvements such as increased bandwidth, reduced signal delay, improved power management, and smaller form-factors. There are many interdependent processing steps involved in the successful integration of TSVs. This article provides a tutorial style review of the following semiconductor fabrication process steps that are commonly used in forming TSVs: deep etching of silicon to form the via, thin film deposition to provide insulation, barrier, and seed layers, electroplating of copper for the conductive metal, and wafer thinning to reveal the TSVs. Recent work in copper electrochemical deposition is highlighted, analyzing the effect of accelerator and suppressor additives in the electrolyte to enable void-free bottom-up filling from a conformally lined seed metal.
Highlights
While Moore’s law has fueled growth in the electronics industry for more than five decades, there has been an increase in both the cost and development time required to miniaturize transistors
This paper provides a conceptual foundation of the function of deep reactive ion etching (DRIE) equipment, as well as traditional etching/passivating mechanisms used to form high-aspect ratio features like Through-silicon vias (TSVs)
A tutorial is provided for the general process steps necessary to fabricate through-silicon vias, an enabling technology for microelectronics integration
Summary
While Moore’s law has fueled growth in the electronics industry for more than five decades, there has been an increase in both the cost and development time required to miniaturize transistors. TSVs enable the stacking of multiple semiconductor chips resulting in packaging microelectronic devices with increased functionality per volume Packaging these sophisticated electronic systems is difficult, and examples of these technical challenges are well described in the literature, especially in the areas of thermal management,[7,8] interconnect compatibility,[9] reliability,[10] and failure modes.[11].
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