Abstract

Based on three-dimensional (3-D) integration technology, a compact sixth-order common-mode noise suppression filter is proposed according to delay line theory. As the important parts of the filter, the on-chip inductors are established by through-silicon vias (TSVs) and the capacitors are realized by double layer interdigital structure. Compared with other relative literatures, the proposed filter has a minimized size of 0.29×0.32 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (0.0203 × 0.0224 λg <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ). And it can suppress the common-mode noise more than 10 dB from 3.8 to 8.6 GHz or more than 20 dB from 4.45 to 7.85 GHz. Meanwhile, the differential signal insertion loss is kept less than 3dB.

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