Abstract
With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and solder bumping processes are the key interconnection technologies that satisfy the former requirements and receive the most attention from the electronic industries. This review mainly includes two directions to get a precise understanding, such as the TSV filling and solder bumping, and explores their reliability aspects. TSV filling addresses the DRIE (deep reactive ion etching) process, including the coating of functional layers on the TSV wall such as an insulating layer, adhesion layer, and seed layer, and TSV filling with molten solder. Solder bumping processes such as electroplating, solder ball bumping, paste printing, and solder injection on a Cu pillar are discussed. In the reliability part for TSV and solder bumping, the fabrication defects, internal stresses, intermetallic compounds, and shear strength are reviewed. These studies aimed to achieve a robust 3D integration technology effectively for future high-density electronics packaging.
Highlights
The most recent technologies in bumping such as TSV filling by molten solder, Cu pillar bumping, solder ball bumping, solder injection bumping, solder paste printing, and bumpless joining are studied to get a better understanding of their implementation in the industries and the associated
For the 3D stacking of Si chips, TSV is achieved by forming vertical holes on a Si wafer by the deep reactive ion etching (DRIE) process, Cu is filled using electroplating, and a solder bump is formed on TSV and reflowed for metallurgical bonding
The problems associated with the high-density packaging such as insulation breakdown of TSVs due to Cu migration, electrical issues of TSVs, and mutual interference of TSV
Summary
Received: 31 August 2021Accepted: 13 October 2021Published: 19 October 2021Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.Licensee MDPI, Basel, Switzerland.Attribution (CC BY) license (https://creativecommons.org/licenses/by/ 4.0/).The recent advancements in digital electronics such as the Internet of Things (IoT), Artificial Intelligence (AI), fifth-generation (5G) communication, and high-performance computer (HPC) demand computers with unbelievable memory, speed, and computation power [1,2]. To meet the demands of growing technology, the number of transistors per unit area in the microchip increases exponentially as per Moore’s law, which is accompanied by the downscaling of the chip size [3]. Currently, major semiconducting companies such as Samsung and TMSC have developed the 5 nm node process for mass production and are looking forward to developing 3 nm nodes in the near future. To fill the gap between
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