Three-dimensional Device Simulation Research Articles

Research on the influence and optimization of sunshade effect on radiative cooling performance

Intense solar radiation is the main reason why radiative cooling is difficult to achieve during the daytime, as the radiative heat flux from the sun will offset the heat emitted by the cooler. Most previous studies have focused on providing coolers with high solar reflectance and high mid-infrared spectral emissivity by designing photonic structures. In this study, a macroscopic sunshade device based on the solar visual motion trajectory is proposed to reduces the direct solar radiation received by the cooler surface through setting a blocking on the solar path, while hardly affecting the radiative capacity of the cooler. Here, we built a three-dimensional sunshade device simulation model based on the surface-to-surface radiative heat transfer module in COMSOL Multiphysics® software, which can effectively improve the cooling performance of the cooler. Then, using polished aluminum plates, black paint-coated cooler, and reflective radi-cool film to test the impact of macroscopic sunshade device based on the solar apparent motion trajectory on improving the cooling performance of difference coolers. The results verified the effectiveness of the proposed sunshade devices in improving radiative cooling performance, and the results showed that the maximum temperature reduction could reach 3.35 °C, 26.96 °C, and 3.42 °C, respectively.

Core-insulator embedded nanosheet field-effect transistor for suppressing device-to-device variations

Nanosheet field-effect transistors (NSFETs) have attracted considerable attention for their potential to achieve improved performance and energy efficiency compared to traditional FinFETs. Here, we present a comprehensive investigation of core-insulator-embedded nanosheet field-effect transistors (C-NSFETs), focusing on their improved performance and device-to-device (D2D) variability compared to conventional NSFETs through three-dimensional device simulations. The C-NSFETs exhibit enhanced direct-current (DC) performance, characterized by a steeper subthreshold slope and reduced off-current, indicating better gate electrostatic controllability. Furthermore, the structural design of C-NSFETs enables to demonstrate a notable resilience against D2D variations in nanosheet thickness and doping concentration. In addition, we investigate the effects of interface traps in C-NSFETs, emphasizing the importance of thermal oxidation processes in the formation of core-insulating layers to maintain optimal device performance.

Three-dimensional quantum-corrected Monte Carlo device simulator of n-FinFETs

Three-dimensional quantum-corrected Monte Carlo device simulator of n-FinFETs

3D modeling of feature-scale fluorocarbon plasma etching in silica

Fluorocarbon dry etching of vertical silica-based structures is essential to the fabrication of advanced complementary metal-oxide-semiconductor and dynamic random access memory devices. However, the development of etching technology is challenged by the lack of understanding of complex surface reaction mechanisms and by the intricacy of etchant flux distribution on the feature-scale. To study these effects, we present a three-dimensional, TCAD-compatible, feature-scale modeling methodology. The methodology combines a level-set topography engine, Langmuir kinetics surface reaction modeling, and a combination of reactant flux evaluation schemes. We calibrate and evaluate our model to a novel, highly selective, etching process of a mathrm {SiO_2} via and a textrm{Ru} hardmask by mathrm {CF_4/C_4F_8}. We adapt our surface reaction model to the novel stack of materials, and we are able to accurately reproduce the etch rates, topography, and critical dimensions of the reported experiments. Our methodology is therefore able to prototype and study novel etching processes and can be integrated into process-aware three-dimensional device simulation workflows.

A Multiscale Simulation Approach for Germanium-Hole-Based Quantum Processor

A multiscale simulation method is developed to model a quantum dot (QD) array of germanium (Ge) holes for quantum computing. Guided by three-dimensional numerical quantum device simulations of QD structures, an analytical model of the tunnel coupling between the neighboring hole QDs is obtained. Two-qubit entangling quantum gate operations and quantum circuit characteristics of the QD array processor are then modeled. Device analysis of two-qubit Ge hole quantum gates demonstrates faster gate speed, smaller process variability, and less stringent requirement of feature size, compared to its silicon counterpart. The multiscale simulation method allows assessment of the quantum processor circuit performance from a bottom-up, physics-informed perspective. Application of the simulation method to the Ge QD array processor indicates its promising potential for preparing high-fidelity ansatz states in quantum chemistry simulations.

Development of an ensemble Monte Carlo simulator for high-power semiconductor devices with self-consistent electromagnetism and GPU implementation

The ensemble Monte Carlo (EMC) method is a powerful and widely used technique for modeling carrier transport in semiconductors in which one can easily take into account band structure and a variety of scattering mechanisms. In the usual implementations of EMC, the semiclassical electron dynamics is coupled self-consistently to the electrostatic field and this suffices for most devices. However, for high power, high current semiconductor device applications the electrostatic approximation is often not adequate and the full electromagnetic (EM) equations must be solved in fully-coupled fashion. We report on the development of a fully self-consistent, time-domain, EM-EMC simulator for two- and three-dimensional device simulations in which we also address a well known drawback of these methods, their computational intensiveness, by producing a GPU implementation.

Transfer learning approach to analyzing the work function fluctuation of gate-all-around silicon nanofin field-effect transistors

With the shrinking of technological nodes, analysis of nanosized-metal-grain pattern-dependent devices is becoming critical; various machine learning (ML) approaches have been utilized to study device characteristic and variability. The inevitable dataset, one of the requisite ML techniques, can be overcome by considering the transfer learning (TL) approach. In this work, an analysis of electrical characteristic affected by work function fluctuation (WKF) with a limited amount of dataset of gate-all-around (GAA) silicon (Si) nanofin (NF) field-effect transistors (FETs) is advanced along with the combination of collected data of GAA Si nanosheet (NS) FETs and TL models. Comparison of the baseline ML model and the proposed TL model shows significant improvement in terms of the values of root mean square error (RMSE) and R2-score. One of applications of this work is to estimate the WKF-induced variability without executing a huge amount of three-dimensional device simulation of GAA Si NF FETs.

Unveiling microscopic carrier loss mechanisms in 12% efficient Cu2ZnSnSe4 solar cells

Understanding carrier loss mechanisms at microscopic regions is imperative for the development of high-performance polycrystalline inorganic thin-film solar cells. Despite the progress achieved for kesterite, a promising environmentally benign and earth-abundant thin-film photovoltaic material, the microscopic carrier loss mechanisms and their impact on device performance remain largely unknown. Herein, we unveil these mechanisms in state-of-the-art Cu2ZnSnSe4 (CZTSe) solar cells using a framework that integrates multiple microscopic and macroscopic characterizations with three-dimensional device simulations. The results indicate the CZTSe films have a relatively long intragrain electron lifetime of 10–30 ns and small recombination losses through bandgap and/or electrostatic potential fluctuations. We identify that the effective minority carrier lifetime of CZTSe is dominated by a large grain boundary recombination velocity (~104 cm s−1), which is the major limiting factor of present device performance. These findings and the framework can greatly advance the research of kesterite and other emerging photovoltaic materials.

Improved Vertical Carrier Transport for Green III-Nitride LEDs Using (In,Ga)N Alloy Quantum Barriers

We report on experimental and simulation-based results using $(\mathrm{In},\mathrm{Ga})\mathrm{N}$ alloy quantum barriers in c-plane green light-emitting diode (LED) structures as a means to improve vertical carrier transport and reduce forward voltage $({V}_{F})$. Three-dimensional device simulations that include random alloy fluctuations are used to understand carrier behavior in a disordered potential. The simulated current density--voltage (J-V) characteristics and modified electron-hole overlap $|{F}_{\mathrm{mod}}{|}^{2}$ indicate that increasing the indium fraction in the $(\mathrm{In},\mathrm{Ga})\mathrm{N}$ quantum barriers leads to a reduced polarization discontinuity at the interface between the quantum barrier and quantum well, thereby reducing ${V}_{F}$ and improving $|{F}_{\mathrm{mod}}{|}^{2}$. Maps of electron and hole current through the device show a relatively homogenous distribution in the $XY$ plane for structures using $\mathrm{Ga}\mathrm{N}$ quantum barriers; in contrast, preferential pathways for vertical transport are identified in structures with $(\mathrm{In},\mathrm{Ga})\mathrm{N}$ barriers as regions of high and low current. A positive correlation between hole (electron) current in the p-side (n-side) barrier and indium fraction reveals that preferential pathways exist in regions of high indium content. Furthermore, a negative correlation between the strain ${\ensuremath{\epsilon}}_{zz}$ and indium fraction shows that high indium content regions have reduced strain-induced piezoelectric polarization in the Z direction due to the mechanical constraint of the surrounding lower indium content regions. Experimentally, multiple quantum well green LEDs with $(\mathrm{In},\mathrm{Ga})\mathrm{N}$ quantum barriers exhibit lower ${V}_{F}$ and blue-shifted wavelengths relative to LEDs with $\mathrm{Ga}\mathrm{N}$ quantum barriers, consistent with simulation data. These results can be used to inform heterostructure design of low ${V}_{F}$, long-wavelength LEDs and provide important insight into the nature of carrier transport in III-nitride alloy materials.

DC Characteristics and Dynamic Properties of Multi-Channel Nanosheet MOSFETs with and without Tungsten Metal Sidewall for Sub-3-nm Technological Nodes

Electrical characteristics of the multi-channel nanosheet (NS) metal-oxide-semiconductor field effect transistors (MOSFETs) with (w/) and without (w/o) the low-resistivity (5.6 × 10–6 Ω-cm) tungsten metal sidewall (MSW) are studied by using an experimentally validated three-dimensional device simulation for sub-3-nm technological nodes. The explored 18-channel n- and p-type NS devices w/ MSW possess a 30-mV/V improvement in the drain-induced barrier lowing, more than 200%-increase in the on-current, about 160%-increase in the gate capacitance, and a 48%-reduction in the delay time, compared with the devices w/o MSW. Our study shows the significance of MSW in vertically stacked multi-channel NS MOSFETs.

On the logic performance of bulk junctionless FinFETs

In this paper, a one-to-one comparison of the logic performance is made between CMOS circuits built with bulk junctionless (JL) FinFETs and that with SOI JL FinFETs for three different technology nodes as per the ITRS roadmap. For such comparison: (i) the rise time and fall time are evaluated from the transient analysis of a CMOS inverter,(ii) the propagation delay per stage for a three-stage ring oscillator is estimated from its frequency of oscillation, and (iii) the static noise margin of a 6 T SRAM cell is evaluated from its butterfly plot. A three-dimensional numerical device and mixed-mode circuit simulator is used for the performance estimation. CMOS circuits implemented with bulk JL devices are found to have comparable logic performance with their SOI JL counterparts.

Prediction of single event upset critical charge and sensitive volume depth by energy deposition analysis of low energy protons

Single Event Upset (SEU) critical charge and sensitive volume depth of 65-nm CMOS bulk SRAM are predicted through energy deposition analysis of low energy protons. The deposited energy distributions of protons calculated by GEANT4 are incorporated into the three-dimensional device simulator to perform the Single Event Effects (SEE) simulation. Based on the analysis of the relationship between the energy deposition distributions and the single event responses, the deposited energy is correlated with the SEU critical charge, and valuable information of the upset sensitive volume depth is provided. Our prediction method is validated by the results of SPICE simulation method as well as experimental data.

Dependence of three-dimensional bottleneck barrier height minimum on threshold voltage fluctuated by ion implantation of source and drain extensions in silicon-on-insulator triple-gate fin-type field-effect transistors

We have investigated the threshold voltage (Vth) fluctuated by ion implantation (I/I) of the source and drain extensions for a leading-edge variability-tolerant device structure using a three-dimensional (3D) process and device simulations. We have previously reported that the fluctuated Vth is characterized by the variation of the minimum value of the 3D bottleneck barrier height (BBH3D,min) of electrostatic potential from the source contact to the corresponding bottleneck points in the entire device. Standardized multiple regression analysis indicated that the 3D position where BBH3D,min exists (BBP3D,min) has only a weak correlation with the Vth. The effect of the BBP3D,min on the Vth is not significantly large; therefore, the Vth can almost be explained by only the value of BBH3D,min over the entire Vth region, despite the drain bias condition.

Three-dimensional exploration of the origin of threshold voltage fluctuation of silicon-on-insulator triple-gate fin-type field-effect transistors caused by ion implantation to source and drain extensions

The origin of the Vth fluctuation induced by ion implantation (I/I) into the source and drain extensions (SDEs) of triple-gate (tri-gate) fin-type field-effect transistors has been three-dimensionally explored by both three-dimensional (3D) process and device simulations. The 3D electrostatic potential distributions in the whole Si channel fin are analyzed, and it is confirmed that the 3D electrostatic potential distribution of the lowest Vth sample is more undulated than that of the highest Vth sample due to implanted arsenic (As+) ions to the SDEs irrespective of the drain bias condition. We found also that the minimum of bottleneck barrier heights (BBHs) in the Si whole channel fin, which is called BBH3D,min, is strongly correlated with the Vth, and therefore is a strong indicator to study the Vth of the device. It now became obvious that the origin of the SDE I/I-induced Vth fluctuation is a variation of BBH3D,min in the whole channel for the first time. The obtained results are beneficial for the research and development of such future devices.

Temperature dependence of single-event transient response in devices with selective-buried-oxide structure

The silicon-on-insulator (SOI) device has been found to possess low leakage current and high operation speed due to reduced internal capacitances. The sensitive volume for charge collection in SOI device is smaller than that in bulk-silicon device, which improves the ability of SOI devices to resist single-event effect (SEE). In spite of these benefits, the SOI device has certain undesirable effects such as the kink effect. To mitigate the kink effect, selective-buried-oxide (SELBOX) SOI structure has been introduced. Space-borne electronic circuits based on SOI technology recently have been used in high radiation and extreme temperature environments. However, temperature affects internal carrier transport process and impact ionization process, which makes single-event transient (SET) pulse widths increased. Most of previous researches regarding temperature dependence of SEE were for SOI floating-body devices. But the influence of operating temperature on SEE of SELBOX SOI devices are yet unclear. In this paper, an SOI floating-body device and a SELBOX SOI device under 90 nm process are established by three-dimensional device simulation, and then temperature dependence of SET response in partially depleted SOI inverter chains is studied by a mixed-mode approach over a temperature range from 200 K to 450 K. Simulation results show that the N-type SELBOX SOI device has a better ability to resist SEE than the floating-body device, while the P-type SELBOX SOI device has the same ability to resist SEE at high linear energy transfer value as the floating-body device. And temperature dependence analysis of charge collection indicates that there is only drift-diffusion process in the N-type SELBOX SOI device. The amount of charge collection in the N-type SELBOX SOI device almost does not change with the increase of temperature. In addition, both the P-type SELBOX SOI device and the P-type floating-body device have a bipolar amplification process. With the increase of temperature, the bipolar amplification process in the substrate turns more serious. However, it suppresses the bipolar amplification process of the source because of SELBOX structure, so that the amount of charge collection is reduced in the drain significantly. According to our simulation results, compared with the floating-body device, the SELBOX SOI device can very well suppress the influence of temperature on SET pulse.

Three-dimensional device simulation of random telegraph noise spectroscopy with Coulomb energy variation of the trap in high-k gate oxide

The random telegraph noise (RTN) time constants, capture (τc) and emission (τe) times, have been extensively used to identify the trap position in the gate oxide by comparing the measured τc-over-τe ratio with the Shockley–Read–Hall (SRH) statistics. However, various factors have been shown to affect the accuracy of the extracted trap depth from the SRH-type models, such as three-dimensional (3D) device electrostatics, atomistic doping, metal gate granularity, and Coulomb energy variation (CEV) of the trap. Focusing on CEV in this work, we assume the trap in gate oxide can be regarded as a floating island and then numerically studied the CEV of the trap with 3D drift-diffusion simulation. Analyzing the simulation data, the extracted trap depth without considering CEV in the SRH statistics are quantitatively compared with the data involved CEV.

The Influence of the Dopant Concentration in a Silicon Film on the Magnetic Sensitivity of SOI Field-Effect Hall Sensors

SOI field-effect Hall sensors (SOI FEHS) are characterized by enhanced functionality but low magnetic sensitivity. The main task of the present study is to search for a way to increase the magnetic sensitivity of such sensors. The results of the study on magnetically sensitive electric characteristics of the SOI FEHSs, obtained using the process and device simulation system Synopsys TCAD, are presented. Three-dimensional device simulation is carried out. The calculated Hall-gate characteristics of the SOI FEHS are obtained, which confirm an earlier proposed sensor physical model according to which, under certain conditions of SOI FEHS operation, a region of increased magnetic sensitivity appears. The influence of the dopant concentration in the sensor channel on magnetic sensitivity is studied. It is shown that the magnetic sensitivity of SOI FEHS triples at a concentration of phosphorus in a working layer of NP = 1016 cm–3. The extended dynamic range of the region of increased magnetic sensitivity (wider than 5 V) permits us to broaden the area of the sensor’s practical application by increasing its noise immunity. The calculated SOI FEHS characteristics agree closely with the earlier published parameters of the experimental devices.

Origin of threshold voltage fluctuation caused by ion implantation to source and drain extensions of silicon-on-insulator triple-gate fin-type field-effect transistors using three-dimensional process and device simulations

The threshold voltage (Vth) fluctuation induced by ion implantation (I/I) in the source and drain extensions (SDEs) of a silicon-on-insulator (SOI) triple-gate (Tri-Gate) fin-type field-effect transistor (FinFET) was analyzed by both three-dimensional (3D) process and device simulations collaboratively. The origin of the Vth fluctuation induced by the SDE I/I is basically a variation of a bottleneck barrier height (BBH) due to implanted arsenic (As+) ions. In particular, a very low and broad Vth distribution in the saturation region is due to percolative conduction in addition to the BBH variation. Moreover, it is surprisingly found that the Vth fluctuation is mostly characterized by the BBH of only a top surface center line of a Si fin of the device. Our collaborative approach by 3D process and device simulations is dispensable for the accurate investigation of variability-tolerant devices. The obtained results are beneficial for the research and development of such future devices.

N-Type Si solar cells with passivating electron contact: Identifying sources for efficiency limitations by wafer thickness and resistivity variation

In this work, the efficiency of n-type silicon solar cells with a front side boron-doped emitter and a full-area tunnel oxide passivating electron contact was studied experimentally as a function of wafer thickness W and resistivity ρb. Conversion efficiencies in the range of 25.0% have been obtained for all variations studied in this work, which cover 150µm to 400µm thick wafers and resistivities from 1Ωcm to 10Ωcm. We present a detailed cell analysis based on three-dimensional full-area device simulations using the solar cell simulation tool Quokka. We show that the experimental variation of the wafer thickness and resistivity at device level in combination with a detailed simulation study allows the identification of recombination induced loss mechanisms. This is possible because different recombination mechanisms can have a very specific influence on the I-V parameters as a function of W and ρb. In fact, we identified Shockley-Read-Hall recombination in the c-Si bulk as the source of a significant FF reduction in case of high resistivity Si. This shows that cells made of high resistivity Si are very sensitive to even a weak lifetime limitation in the c-Si bulk. Applying low resistivity 1Ωcm n-type Si in combination with optimized fabrication processes, we achieved confirmed efficiency values of 25.7%, with a VOC of 725mV, a FF of 83.3% and a JSC of 42.5mA/cm2. This represents the highest efficiency reported for both-sides contacted c-Si solar cells. Thus, the results presented in this work demonstrate not only the potential of the cell structure, but also that a variation of the wafer thickness and resistivity at device level can provide deep insights into the cell performance.

Very low and broad threshold voltage fluctuation caused by ion implantation to silicon-on-insulator triple-gate fin-type field effect transistor using three-dimensional process and device simulations

The threshold voltage (Vth) fluctuation induced by the ion implantation to the source and drain extensions (SDE) of a silicon-on-insulator (SOI) triple-gate (tri-gate) fin-type field-effect transistor (FinFET) was analyzed for the first time with the use of realistic positional information of discretely doped ions by both three-dimensional (3D) process and device simulations. Interestingly, it was found that the Vth fluctuation induced by SDE ion implantation has a very low and broad distribution on the low-Vth side even in the case of a robust device structure such as SOI tri-gate FinFET. Furthermore, for the first time, it was quantitatively demonstrated using a proposed cluster percolation model that the origin of the very low and broad Vth fluctuation is the conductive percolation among unintentionally doped ions in the channel region of the device. These results would contribute to the realization of robust transistors.