Threading Dislocation Density Research Articles

Dislocation Filter Based on LT-GaAs Layers for Monolithic GaAs/Si Integration.

The use of low-temperature (LT) GaAs layers as dislocation filters in GaAs/Si heterostructures (HSs) was investigated in this study. The effects of intermediate LT-GaAs layers and of the post-growth and cyclic in situ annealing on the structural properties of GaAs/LT-GaAs/GaAs/Si(001) HSs were studied. It was found that the introduction of LT-GaAs layers, in combination with post-growth cyclic annealing, reduced the threading dislocation density down to 5 × 106 cm-2, the root-mean-square roughness of the GaAs surface down to 1.1 nm, and the concentration of non-radiative recombination centers in the near-surface GaAs/Si regions down to the homoepitaxial GaAs level. Possible reasons for the improvement in the quality of near-surface GaAs layers are discussed. On the one hand, the presence of elastic deformations in the GaAs/LT-GaAs system led to dislocation line bending. On the other hand, gallium vacancies, formed in the LT-GaAs layers, diffused into the overlying GaAs layers and led to an increase in the dislocation glide rate. It was demonstrated that the GaAs/Si HSs obtained with these techniques are suitable for growing high-quality light-emitting HSs with self-assembled quantum dots.

Degradation study on triple junction inverted metamorphic InGaP/InGaAs-GaAsP MQW/InGaAs multiple quantum well solar cell using advanced physical models

In this work, we investigated triple-junction (3J) solar cell with inverted metamorphic structure, used for space application. Unlike conventional inverted metamorphic (IMM) InGaP/GaAs/In0.30Ga0.70As, we propose inclusion of MQW in the middle GaAs for better spectral response and radiation resistance. Using Crosslight APSYS, the important non-idealities such as surface recombination velocity (SRV) and threading dislocation density (TDD) are defined and its effect on device characteristics are presented. For TDD upto 1 × 105 cm−2 in the graded buffer InGaP and the bottom In0.30Ga0.70As subcell, the influence on device characteristics has obtained to be very marginal. Under 1-sun AM0 spectrum, the proposed triple junction InGaP/InGaAs-GaAsP MQW/InGaAs inverted metamorphic solar cell (3J MQW IMM) attained a maximum efficiency of 37.15% (without SRV) and 36.39% (at 104 cm/s SRV).

Strain Relaxation of Si/SiGe Heterostructures by a Geometric Monte Carlo Approach

Solid‐state‐based quantum technologies, such as electronic spin‐qubits, constitute a leading approach to the realization of quantum computation. Electronic spin‐qubits hosted in semiconductor heterostructures demand the highest crystalline quality, specifically with respect to the structure and formation of in‐plane misfit dislocations (MDs). Here, the formation mechanisms of MD networks in such Si/SiGe heterostructures are investigated. For this purpose, strained Si layers on relaxed Si0.7Ge0.3 with thicknesses above the critical thickness are grown by molecular beam epitaxy to allow for the formation of MDs. MDs are mapped out by electron channeling contrast imaging and the experimental results are compared to MD networks calculated by Monte Carlo simulations. The simulations show that the ratio between the threading dislocation density (TDD) and the average length of MDs is a constant for a given set of parameters, here 2.9 for sufficiently large dislocation statistics and simultaneous extension of MDs. Further, the fractal dimension of the MD network determined by the box‐counting method as an alternative quantity to characterize MD networks is introduced. This allows to infer the formation mechanism of MDs in real devices and hence the quantification of resulting average relaxation within the Si‐quantum well.

Radiative Recombination and Carrier Injection Efficiencies in 265 nm Deep Ultraviolet Light‐Emitting Diodes Grown on AlN/Sapphire Templates with Different Defect Densities

The electro‐optical characteristics of deep ultraviolet light‐emitting diodes (DUV LEDs) emitting at 265 nm and grown on AlN/sapphire templates with different threading dislocation densities, i.e., high‐temperature annealed (HTA) AlN, epitaxially laterally overgrown (ELO) AlN, and HTA‐ELO AlN are analyzed. The external quantum efficiency of each individual device is separated into maximum radiative recombination efficiency, carrier injection efficiency, and light extraction efficiency. This is achieved by combining an ABC‐model‐based fit of the current‐dependent external quantum efficiency together with calibrated Monte Carlo ray‐tracing simulations. A maximum radiative recombination efficiency between 50% and 60% is estimated for DUV LEDs grown on ELO and HTA‐ELO AlN/sapphire, whereas the values for devices grown on HTA AlN/sapphire are around 45%. The extracted radiative recombination efficiency does not scale with the measured threading dislocation density (TDD), even when accounting for the inhomogeneous TDD in the AlN base layers. This discrepancy is attributed to the formation of dislocation half‐loops introduced by additional compressive strain caused by the HTA process and may result in the formation of additional nonradiative recombination centers in the AlGaN multi‐quantum well region. In addition, the carrier injection efficiency values ranging from 45% to 55% are determined for devices grown on all three templates.

Crystalline Quality and Surface Morphology Improvement of Face-to-Face Annealed MBE-Grown AlN on h-BN

In this study, AlN epilayers were grown by ammonia-assisted molecular beam epitaxy on 3 nm h-BN grown on c-sapphire substrates. Their structural properties were investigated by comparing as-grown and postgrowth annealed layers. The role of annealing on the crystalline quality and surface morphology was studied as a function of AlN thickness and the annealing duration and temperature. Optimum annealing conditions were identified. The results of X-ray diffraction showed that optimization of the annealing recipe led to a significant reduction in the symmetric (0 0 0 2) and skew symmetric (1 0 -1 1) reflections, which was associated with a reduction in edge and mixed threading dislocation densities (TDDs). Furthermore, the impact on the crystalline structure of AlN and its surface was studied, and the results showed a transition from a surface with high roughness to a smoother surface morphology with a significant reduction in roughness. In addition, the annealing duration was increased at 1650 °C to further understand the impact on both AlN and h-BN, and the results showed a diffusion interplay between AlN and h-BN. Finally, an AlN layer was regrown on the top of an annealed template, which led to large terraces with atomic steps and low roughness.

Study of Defects and Nano-patterned Substrate Regulation Mechanism in AlN Epilayers.

The high crystal quality and low dislocation densities of aluminum nitride (AlN) grown on flat and nano-patterned sapphire substrate that are synthesized by the metal-organic chemical vapor deposition (MOCVD) method are essential for the realization of high-efficiency deep ultraviolet light-emitting diodes. The micro-strains of 0.18 × 10-3 cm-2 for flat substrate AlN and 0.11 × 10-3 cm-2 for nano-patterned substrate AlN are obtained by X-ray diffractometer (XRD). The screw and edge dislocation densities of samples are determined by XRD and transmission electron microscope (TEM), and the results indicate that the nano-patterned substrates are effective in reducing the threading dislocation density. The mechanism of the variation of the threading dislocation in AlN films grown on flat and nano-patterned substrates is investigated comparatively. The etch pit density (EPD) determined by preferential chemical etching is about 1.04 × 108 cm-2 for AlN grown on a nano-patterned substrate, which is slightly smaller than the results obtained by XRD and TEM investigation. Three types of etch pits with different sizes are all revealed on the AlN surface using the hot KOH etching method.

Confinement of Electrons at the LaInO3/BaSnO3 Heterointerface

AbstractThe properties of the conductance at the LaInO3/BaSnO3 heterointerface are reported. The heterointerface is formed by covering the semi‐insulating BaSnO3:La thin films with 10 nm LaInO3 films, which are all epitaxially grown on NdScO3 substrates. Structural properties of BaSnO3 thin films are investigated by means of X‐ray diffraction and transmission electron microscopy and exhibit a threading dislocation density of 6 × 1010 cm−2. Via capacitance–voltage (C–V) measurements, clear evidence is present for the accumulation of electrons at the interface within 2.5 nm in the BaSnO3 layer, confirming the formation of a 2D electron gas (2DEG). Additionally, temperature dependent Hall effect measurements reveal a semiconducting behavior of the electron density of the 2DEGs. The room temperature mobility of 22 cm2 V−1 s−1 at an electron density of 4 × 1013 cm−2 is found to increase as the temperature decreases to 25 K.

Room-temperature nonradiative recombination lifetimes in c-plane Al1−xInxN epilayers nearly and modestly lattice-matched to GaN (0.11 ≤ x ≤ 0.21)

Lattice-matched Al1−xInxN / GaN heterostructures with InN mole fraction (x) of 0.18 have attracted considerable interest for use in GaN-based optoelectronic devices. Because the light emission efficiency (ηemission) of Al1−xInxN alloys is far less than that of InxGa1−xN, understanding its causes is essential. For this purpose, room-temperature photoluminescence lifetime (τPLRT), which almost represents the nonradiative recombination lifetime that limits the internal quantum efficiency in low ηemission semiconductors, of c-plane Al1−xInxN epilayers nearly and modestly lattice-matched to GaN (0.11≤x≤0.21) was examined. For the epilayers grown on low threading dislocation density (TDD) GaN substrates (≪107cm−2), τPLRT principally decreased with increasing x, indicating a progressive increase in the concentration of nonradiative recombination centers (NRCs), NNRC. One of the probable causes is the growth temperature (Tg) reduction that is indispensable to incorporate more In, because in insufficient Tg regime higher Tg is preferred for enhancing the surface migration of adatoms to decrease the concentrations of vacancies that compose NRCs. The Al1−xInxN epilayers of the same x but grown on high TDD (>108cm−2) GaN-on-sapphire templates exhibited shorter τPLRT. Because the diffusion length of minority carriers was nearly zero in the Al1−xInxN epilayers, the shorter τPLRT indicates higher bulk NNRC in high TDD epilayers. The Al1−xInxN epilayers of considerably rough surface morphologies exhibited spatially inhomogeneous τPLRT, implying that excited carriers recombined everywhere at InN-rich to InN-poor portions, where NNRC were likely lower to higher, respectively, than the average due to the deviations in the surface stoichiometry at various non-c-plane surfaces at a given Tg.

∼8.5 μm-emitting InP-based quantum cascade lasers grown on GaAs by metal-organic chemical vapor deposition

Room-temperature, pulsed-operation lasing of 8.5 μm-emitting InP-based quantum cascade lasers (QCLs), with low threshold-current density and watt-level output power, is demonstrated from structures grown on (001) GaAs substrates by metal-organic chemical vapor deposition. Prior to growing the laser structure, which contains a 35-stage In0.53Ga0.47As/In0.52Al0.48As lattice-matched active-core region, a ∼2 μm-thick nearly fully relaxed InP buffer with strained 1.6 nm-thick InAs quantum-dot-like dislocation-filter layers was grown. A smooth terminal buffer-layer surface, with roughness as low as 0.4 nm on a 10 × 10 μm2 scale, was obtained, while the estimated threading-dislocation density was in the mid-range × 108 cm−2. A series of measurements, on lasers grown on InP metamorphic buffer layers (MBLs) and on native InP substrates, were performed for understanding the impact of the buffer-layer's surface roughness, residual strain, and threading-dislocation density on unipolar devices such as QCLs. As-cleaved devices, grown on InP MBLs, were fabricated as 25 μm × 3 mm deep-etched ridge guides with lateral current injection. The results are pulsed maximum output power of 1.95 W/facet and a low threshold-current density of 1.86 kA/cm2 at 293 K. These values are comparable to those obtained from devices grown on InP: 2.09 W/facet and 2.42 kA/cm2. This demonstrates the relative insensitivity of the device-performance metrics on high residual threading-dislocation density, and high-performance InP-based QCLs emitting near 8 μm can be achieved on lattice-mismatched substrates.

The optimal threading dislocation density of AlN template for micrometer-thick Al0.63Ga0.37N heteroepitaxy

Growth of Si-doped AlN and of Al0.63Ga0.37N on high quality AlN templates grown by HVPE has been investigated. The strain state of Si-doped AlN is thickness-dependent due to the surface-mediated dislocation tilt which induces a tensile strain component. At very low dislocation density in the AlN buffer strain relaxation in micrometer-thick Al0.63Ga0.37N layers is dominated by generation of additional dislocations. As a result, the final threading dislocation density and the surface roughness increase significantly. For a 1.6 μm Al0.63Ga0.37N on 3.4 μm Si-doped AlN bi-layer structure, the optimal threading dislocation density (TDD) of the AlN:Si buffer is estimated to be 7 × 108 cm−2, where the low TDD can be still transferred from the buffer to the thick AlGaN heterostructure without generation of many new dislocations.

High Quality Ge Growth on Si (111) and Si (110) by Using Reduced Pressure Chemical Vapor Deposition

Heteroepitaxial growth of Ge on Si has great interest for various optoelectronic applications such as Ge photodiodes(1). However 4.2% of lattice mismatch causes dislocation formation and island growth. High quality Ge(001) growth techniques are reported in ref.(2-4). Moreover, Ge(111) surface is also interesting because of higher carrier mobility(5). Furthermore, Ge(110) is preferred orientation of virtual substrates for epitaxial graphene growth(6). In the case of the Ge deposition on Si(111) and Si(110) substrates, it seems that the process conditions used for Ge growth on Si(001) are not suitable to realize high crystallinity and smooth surface (7). In this paper, we present a method of high quality and smooth Ge layer growth on Si(111) and Si(110), which is the same level as the Ge growth on Si(001).Epitaxial growth of Ge on Si(111) and Si(110) is carried out using a reduced pressure chemical vapor deposition system. After HF last clean, a wafer is baked at 1000°C and cooled down to 600°C in H2 and further to 300-550°C in N2 to form a hydrogen-free Si surface. Then a 100 nm thick Ge layer is deposited as a seed layer using GeH4 with N2 carrier gas. Afterward the wafer is heated up to 450-650°C in H2 and the main part of Ge is deposited using a H2-GeH4 gas mixture. For threading dislocation density (TDD) reduction, annealing at 800°C in H2 is performed for several times (cyclic annealing) by interrupting the Ge growth. Atomic-force microscopy (AFM) is used for surface roughness analysis. Scanning transmission electron microscopy (STEM) and X-ray diffraction (XRD) are used for structural characterization of the Ge layer. Secco defect etching combined with angle view scanning electron microscopy (SEM) or optical microscope is used for TDD evaluation.Figure 1(a,b) summarize the root mean square (RMS) roughness of Ge(111) and Ge(110) seed layers grown at 300-550°C before and after postannealing at 600-800°C. If the growth temperature is lower than 350°C for Ge(111) and 400°C for Ge(110), a significant increase of the surface roughness is observed after postannealing at 700°C and 800°C, respectively. For both crystal orientations, the lowest RMS roughness is observed by depositing at 450°C for as deposited and postannealed samples. The maintained RMS roughness even after postannealing at 800oC may be indicating good crystal quality even at as deposited condition.To confirm the influence of the growth temperature on the crystallinity, cross section TEM images of the Ge(111) and the Ge(110) seed layers deposited at 300°C and 450°C are shown in Fig. 2(a-d). In the case of Ge growth at 300°C (Fig. 2(a,b)), a very high density of stacking faults (SF) and high surface roughness are observed for both crystal orientations. In contrast, by depositing at 450°C (Fig. 2(c,d)), lower SF density in the Ge layer is observed compared to that at 300°C. By postannealing, an improvement of crystallinity is observed for the Ge seed layers deposited at 450°C. However, in the case of 300°C, the crystallinity cannot be improved by the postannealing, because a too high density of dislocations and SF may cause irregular Ge atom migration. As the result, surface roughening occurs.Figure 3(a,b) show AFM surface roughness images after 5 μm-thick Ge(111) and Ge(110) deposited with cyclic annealing at 800°C, respectively. Clear terraces of ~0.3 and ~0.2 nm, whose heights are close to those of Ge(111) bilayer and Ge(110) monolayer, are observed, respectively. RMS roughness of the Ge(111) and the Ge(110) are 0.51 and 0.35 nm, respectively. These RMS roughnesses are comparable to a level reported for Ge (001) in ref.(1).Figure 4 shows TDD of Ge(111) and Ge(110) surfaces as a function of the Ge thickness deposited with cyclic annealing on Si(111) and Si(110) substrates. For both orientations, TDD of ~4×108 cm-2 is obtained for 500 nm-thick samples. With increasing the Ge thickness, the TDD is reduced and levels below TDD of ~5×106 cm-2 are achieved for both Ge (111) and Ge(110) for 5 μm-thick Ge.These methods enable high quality virtual substrate fabrication not only for (001) surfaces but also for (111) and (110) orientation without a chemical mechanical polishing process. References Lischke et al. Nature Photonics15 (2021) 925Yamamoto et al. Solid-State Electron. 60 (2010) 2Yamamoto et al. Semicond. Sci. Technol. 33 (2018) 124007 M. Hartmann et al. J. Appl. Phys. 95 (2004) 5905 H. Lee et al. IEDM Tech. Digest (2009) 09-457J-H. Lee et al. Science 344 6181(2014) 286M. Hartmann et al. J. Cryst. Growth 310 (2008) 5287 Figure 1

Ge Nano-Heteroepitaxy: From Nano-Pillars to Thick Coalesced Layers

Ge co-integration with Si has always attracted a lot of attention. Thanks to its superior electronic properties, Ge can be used as a channel material in p-type Metal Oxide Semiconductor transistors (high hole mobility) or low power devices such as tunnelling field effect transistors (steep sub-threshold swing operation). Furthermore, Ge is a key enabler in numerous optoelectronic devices (light emitters and photo-detectors). The epitaxial growth of Ge on Si is far from being lattice matched, with a 4.2% difference between Si and Ge, making high quality growth difficult, especially for thick layers.Several schemes have been explored in the literature to obtain thick, good crystalline quality Ge layers, such as a low temperature/high temperature approach followed by a cyclic anneal which yielded flat, slightly tensile strained thick Ge layers with threading dislocation densities around 107 cm-2. Other methods based on epitaxial lateral overgrowth, aspect ratio trapping and 3D heteroepitaxy of Ge films on patterned Si substrates have shown promising results thanks to defect blocking against sidewalls or their containment in certain directions. However, some planar defects were still present at the coalescence fronts with those growth methods.Another interesting method is to perform a heteroepitaxy of Ge in nanometer-size Si windows surrounded by SiO2. Lee et al [1] succeeded in obtaining high quality Ge layers using nano-heteroepitaxy but did not go further in the analysis of defects generated with such an approach. In a previous work [2], we were able to obtain smooth, fully strain relaxed Si0.76Ge0.24 layers with heteroepitaxial growth in nanometer-size Si windows surrounded by SiO2. In that case, SiGe epitaxial growth was carried out on a patterned substrate with a regular array of nanometre-size seed pillars, and growth fronts from individual nano-pillars coalesced to form complete 2D layers. However, planar defects such as stacking faults and twins were present in the final layers. In this work, we wanted to test this growth approach for pure Ge and provide an in-depth analysis of any defects generated.An original process flow based on diblock copolymer patterning was thus used to fabricate nanometer-size SiO2 based templates for growth (Figure 1a). The nano-heteroepitaxy of 2D Ge layers on these templates was performed at 90 Torr, using GeH4 as a precursor, and compared to growth on blanket Si.Ge nano-pillar growth was first investigated, with a delayed Ge growth found at 400°C. Nano-pillars obtained after the growth of 35 nm of Ge were not as homogeneous and well-defined as the 20 nm high SiGe nano-pillars in Ref. [3]. Raising the growth temperature to 600°C resulted in a highly selective and uniform process, with homogeneous and well-defined Ge nano-pillars for growth nominally 20 nm thick. The expected nano-pillar coalescence scheme was also observed at this growth temperature [3]. Transmission Electron Microscopy (TEM) imaging of the 20 nm sample grown at 600°C showed facetted Ge nano-pillars, with numerous 90° edge dislocations at the Ge/Si interface as expected given the low critical thickness of Ge on silicon (4 nm, typically) and the 20 nm nano-pillar width (Figure 1b).Ge thick layers were then grown with a low temperature/high temperature strategy on bulk and nano-patterned substrates for a benchmark of the nano-heteroepitaxy approach. Atomic Force Microscopy (AFM) showed micrometric-size holes at the surface for Ge layers grown on nano-patterned substrates. This might be due to an incomplete coalescence of the thick Ge layers, which were by contrast very smooth on bulk Si (Figure 1c). TEM analysis of a 600 nm thick Ge layer grown on Ge nano-pillars suggested that coalescence resulted in planar defects such as twins and stacking faults starting at the oxide walls, as found for SiGe pillars in previous studies, in addition to edge dislocations at the Ge/Si interface. Despite these morphological differences, similar structural properties (in terms of degree of strain relaxation and Full Width at Half Maximum of the Ge spot along the in-plane direction) were inferred from X-Ray Diffraction (XRD) for layers grown on nano-patterned and bulk substrates (Figure 1d).[1] J. Lee et al., J. Cryst. Growth 301–302, 330 (2007).[2] M. Mastari et al., Nanotechnology 29, 275702 (2018).[3] M. Mastari et al., ECS J. Solid State Sci. Technol. 8, 180 (2019). Figure 1

Viewing SiGe Heterostructure for Qubits with Dislocation Theory

SiGe/Si/SiGe heterostructure serves as one of the ideal semiconductor material system to build large scale electron spin qubits[1]. To further push the scalability and extend the coherence times of qubits built on SiGe/Si/SiGe heterostructures, there are several factors to improve, one of that is the lattice homogeneity of strained Si. One source of lattice homogeneity break down are dislocations. Due to the difficulties of high quality SiGe bulk crystal growth [2-3], relaxed SiGe is commonly grown on Si substrates by epitaxy. Viewing the SiGe/Si/SiGe heterostructure on native Si substrate, dislocations half loops form unavoidably because of the misfit between SiGe and the Si substrate. These dislocation half loops consist of threading segments extending through the whole heterostructure (figure 1 (a) and (c)) [4]. Due to the stress caused by the strained Si quantum well layer, the threading dislocations can be driven to glide, resulting in additional misfit segments in the lower interface of strained Si layer when the critical thickness is exceeded (figure 1 (b)) [5]. The extension of these misfit segments is blocked when they meet other perpendicular dislocations (figure 1 (d)) [6]. These misfit dislocations destroy strain uniformity and cause tilt inside the Si layer, resulting in a distortion of the valley splitting and ultimately, reducing the coherence time of qubits [7-8].In this work, we present the observation of dislocations in SiGe/Si/SiGe heterostructures for qubit application by plan-view TEM (Figure 1 (right)). Here, the experimental observations agree with dislocation theory that threading dislocations (some are marked by (b)) will glide and elongate to have misfit segments (some are marked by (c)) in the interface when two requirements are fulfilled: misfit exists between epitaxial layer and substrate; critical thickness is exceeded. When the misfit dislocations meet perpendicular misfit dislocation line, they are blocked since the thickness is not enough to glide over it [6]. This is the case in figure 1 right marked by (d). Due to the misfit segment generation and blocking effects, the misfit dislocation spacing is proportional to the threading dislocation density both theoretically and experimentally. These misfit dislocations bring local strain field around them [9], which disturb the desired homogeneous strain field by misfit. Therefore, misfit dislocation generation needs to be suppressed if one wants to achieve homogeneous strain in Si thin layer in large scale.According to Matthews-Blakeslee theory, one can avoid the formation of misfit dislocations in the Si interface by controlling the strained layer within the critical thickness. The critical thickness of Si on Si0.7Ge0.3 is calculated as 8.5 nm. The Electron channeling contrast images of Si with difference thickness 10 nm and 5 nm grown on high threading dislocation relaxed Si0.7Ge0.3 buffer at 700°C by reduced pressure chemical vapor deposition in Figure 2 are collaborating with theory: obviously misfit dislocation appear in 10 nm Si on relaxed Si0.7Ge0.3 (Figure 2 (left)) and no misfit dislocation are presented in 5 nm Si on Si0.7Ge0.3 (Figure 2 (right)).Our results show that dislocation generation and movement needs to be taken into consideration to further develop SiGe heterostructure based qubits.

(Invited) Deep Level Defects in AlN Studied By UV-Visible Spectroscopy

The ultrawide-bandgap (UWBG) AlGaN alloy system is emerging as a promising material for next generation power semiconductor devices. The increase in bandgap as the alloy composition is varied from the binary endpoints GaN to AlN leads to an increase in the critical electric field, which is a key parameter determining the performance of power semiconductor devices. As development of GaN and SiC materials for high-frequency and high-power devices reaches a state of maturity, pursuit of improved device performance is generating interest in UWBG materials with larger bandgaps. High Al composition AlGaN alloys, in addition to offering increased critical electric fields, offer prospects for improved device performance in high temperature operation. Fundamental challenges to the development of AlGaN-based devices, such as controllable doping, electrical contacts, and effective passivation, remain, but a variety of power devices have already been demonstrated (1-3).Point defects strongly affect the material properties of semiconductors, with important consequences for device performance. In traditional semiconductors, such as Si, point defects have been studied extensively, and point defect engineering methods have been developed to enhance device performance. However, the properties of point defects in UWBG materials are not as well understood. Point defects may be introduced during device growth, fabrication, and operation. On the one hand, intentionally introduced impurities (dopants) are critical to the control of electrical transport, while on the other hand, unintentionally introduced impurities may act deleteriously as carrier traps or recombination centers. In AlGaN, compensation by deep level, native point defects or unintentionally incorporated impurities limits achievable free carrier concentrations in electronic devices, while defects and their complexes affect the optical properties in optoelectronic devices. Since point defects exert such a strong influence on material properties, and are often responsible for device degradation, knowledge of their formation mechanisms and material effects are essential to develop strategies for the required control of point defect concentrations (4).In this work, we studied the optical signatures of deep level defects in single crystal AlN substrates. AlN possesses a high thermal conductivity and a close lattice match to high Al composition alloys, which make it an excellent substrate choice for growth of AlGaN-based power electronic and optoelectronic devices. High-quality, 2-inch diameter AlN substrates with average threading dislocation densities below 103 cm-2 were recently demonstrated (5). However, high optical absorption in the ultraviolet-C (UV-C) region was observed in AlN substrates grown by physical vapor transport (PVT), due to a deep level absorption band related to the carbon impurity. This absorption band negatively impacts the efficiency of UV-C optoelectronic devices that require light propagation through the substrate. In order to reduce the unwanted UV-C absorption, we studied the optical properties of double-side polished, 2-inch, c-plane AlN substrates by ultraviolet-visible (UV-Vis) spectroscopy and developed strategies for point defect control. Spatially uniform absorption coefficients below 30 cm-1 at 265 nm were demonstrated across 2-inch substrates (6). In this talk, UV-Vis absorption, photoluminescence (PL) emission, and PL excitation spectra will be presented and correlated with measured impurity concentrations from secondary ion mass spectrometry (SIMS) data, in order to identify deep level defects in AlN. Finally, the mechanisms for reduction of UV-C absorption in PVT AlN will be discussed.References R. J. Kaplar, A. A. Allerman, A. M. Armstrong, M. H. Crawford, J. R. Dickerson, A. J. Fischer, A. G. Baca, and E. A. Douglas, ECS J. Sol. State Sci. and Technol. 6(2), Q3061 (2017).P. H. Carey IV, F. Ren, A. G. Baca, B. A. Klein, A. A. Allerman, A. M. Armstrong, E. A. Douglas, R. J. Kaplar, P. G. Kotula, and S. J. Pearton, IEEE Trans. Semicond. Manuf. 32(4), 473 (2019).A. G. Baca, A. M. Armstrong, B. A. Klein, A. A. Allerman, E. A. Douglas, and R. J. Kaplar, J. Vac. Sci. Technol. A 38, 20803 (2020).S. Washiyama, P. Reddy, B. Sarkar, M. H. Breckenridge, Q. Guo, P. Bagheri, A. Klump, R. Kirste, J. Tweedie, S. Mita, Z. Sitar, and R. Collazo, J. Appl. Phys. 127, 105702 (2020).R. Dalmau, J. Britt, H. Fang, B. Raghothamachar, M. Dudley, and R. Schlesser, Mater Sci. Forum 1004, 63 (2020).R. Dalmau, S. Kirby, J. Britt, and R. Schlesser, ECS Trans. 104(7), 49 (2021).

(Digital Presentation) Epitaxially Grown of SiGe on Ge Microbridge and Observation of Strong Resonant Light Emission

Introduction Ge has been attracting attention for the realization of intra chip optical integrated circuits. In particular, the introduction of tensile strain by epitaxial growth of Ge on Si substrate improves the direct transition probability by shifting the Γ-valley, resulting in an increase in luminescence efficiency. Furthermore, by forming Ge microbridge structure, the larger uniaxial tensile strain can be induced into the freestanding Ge, which is expected to further improve the luminescence efficiency [1]. However, when the stronger tensile strain is applied to Ge, the emission wavelength shifts significantly to the longer wavelength. In order to arbitrary control the emission wavelength to the shorter, especially within the telecommunication wavelength band, introduction of SiGe/Ge heterostructures in the microbridge is considered to be one of the most proper ways. In this work, we attempt to grow the strained SiGe layer on the Ge microbridge and observe the shorter wavelength light emission from the strained SiGe. Moreover, it has been shown that Fabry-Perot resonance takes place in the Ge microbridge structure owing to the side wall reflection [2], leading to the strong resonant luminescence peaks. Here also we observe the resonant light emission from the SiGe/Ge microbridge structure. Experimental Methods A Ge layer was grown on a Si(100) wafer by solid-source molecular beam epitaxy (MBE) with using so-called two-step growth method. First, a 40-nm-thick buffer layer was grown at a low temperature of 350 °C. Then, 500 nm thick Ge layer was grown at 600 °C. Finally, thermal annealing was performed in situ at a temperature of 800 °C for 10 min to reduce the threading dislocation density in Ge layers. After the MBE growth, patterning of the microbridge structure was performed by standard photolithography process and inductively coupled plasma reactive-ion dry etching. Si beneath the microbridge was then removed to form freestanding structures by KOH wet etching. After fabrication of the Ge microbridge, 60 nm thick Si0.2Ge0.8 layer was directly grown on the Ge microbridge at 350 °C. Results and Discussion SEM observation showed that fine microbridge structure remains unchanged after the Si0.2Ge0.8 layer overgrowth on the Ge microbridge. Raman measurements confirmed that the grown SiGe has tensile strain originated from the lattice mismatch between the Si0.2Ge0.8 and underneath Ge, indicating that elastic strain relaxation did not occur. A PL spectrum obtained from the central position of the Si0.2Ge0.8 microbridge exhibits strong light emission in the wavelength range from 1500 to 2000 nm. This is thought to be originated both from SiGe and Ge layers. The PL intensity around shorter wavelength region is significantly increased after the Si0.2Ge0.8 epitaxial growth compared to that before the growth, indicating that the SiGe growth is contributing to the light emission at the telecommunication band. It is noted that a PL spectrum obtained in the unpatterned area from the same sample has almost no light emission, indicating that the microbridge structure is very promising for obtaining the strong light emission. Also it is remarkable that the resonance peaks can be obviously observed. The calculation confirmed this resonance is due to the reflection between side walls of the microbridge. From these results, we can say that the SiGe/Ge heterostructure based microbriges serve as wavelength-controllable high efficiency light sources on Si.This work was partially supported by JSPS KAKENHI (Nos. 19H02175, 19H05616 and 20K21009).[1] M. J. Suess et al, Nat. Photonics 7: 466, 2013[2] Peiji Zhou et al 2018 Jpn. J. Appl. Phys. 57 04FH10 Figure 1

Stress Engineering in Germanium-Silicon Heterostructure Using Surface Activated Hot Bonding

The manufacturing of heterostructures is interesting in fields such as photonics(1), solar energy production(2) and quantum technologies(3). This paper, dedicated to germanium on silicon heterostructure manufacturing and stress engineering, builds up on Ref. (4) findings.We are using the differences in terms of coefficients of thermal expansion (CTE) between germanium and silicon, to induce a tensile stress in a thin germanium layer transferred by the Smart CutTM [1] technique onto a silicon substrate. In this approach, a bulk germanium wafer is directly bonded on a bulk silicon wafer, using surface activated bonding (SAB)(5,6). Process integration advantages are the low defect density of bulk germanium and the tensile stress that can be tuned using the bonding temperature.The adherence of SAB was high during bonding at relatively high temperatures (~250°C). Without any further heat treatment, the adherence was found to be 3500mJ/m2 by the double cantilever beam method (under prescribed displacement control and in an anhydrous atmosphere). This remarkable adherence prevented the Ge/Si heterostructure from sliding, debonding and cracking (7). The CTE difference could thus generate a large amount of tensile stress during the heterostructure cooling and splitting steps.First of all, using finite elements simulation, a model was designed to predict the bow and the in-plane internal stress after bonding and cooling of the heterostructure. Thanks to it, we could also evaluate those two values after layer transfer (splitting step). This numerical approach was more accurate than the former analytic method (Timoshenko), which did not include the non-linearity of CTE with temperature and for large displacements. Figure 1 shows the bow and the in-plane stress expected for a bonding at 250°C of, respectively, a Si/Si homostructure (Figure1.a) and a strained Ge/Si heterostructure (Figure1.b), when cooled down to room temperature. The former is flat while the bow of the latter is large indeed.Then, based on indications collected from simulations, we performed the bonding of a Si/Si homostructure in an EVG®ComBond® at 250°C. The same bonding conditions were used for an implanted germanium on silicon heterostructure. As shown in Figure 2, both bond pairs exhibited a bow close to that from FE simulations.After that, a splitting step was carried out, resulting in a thin germanium film on a silicon wafer (200mm), as shown in Figure 3. The film was transferred almost to the whole surface. The bow after splitting was of 10µm, a value not so far from the simulated value of 28.6 µm.As far as tensile stress was concerned, we used X-Ray Diffraction to gain access to the lattice parameter deformation and thus the tensile stress, 0.05% and 72 MPa, respectively (Figure 4). In comparison, FE simulation gives us 107 MPa of tensile stress after splitting. The main advantage of our approach is the lack of misfit dislocations in the Ge film, at variance with Ge epitaxy on Si (with a threading dislocations density typically around 107 cm-2, then).The presentation will focus, first, on the simulation tool and the manufacturing process used to fabricate such stressed germanium films. Then, stress calculus will be detailed. Finally, TEM imaging of cross-sections, XRD and bow measurements will help us better understand the specificities of such thin Ge films transferred on Si bulk wafers. Higurashi E. Heterogeneous integration based on low-temperature bonding for advanced optoelectronic devices. Jpn J Appl Phys. 1 avr 2018;57(4S):04FA02.King RR, Law DC, Edmondson KM, Fetzer CM, Kinsey GS, Yoon H, et al. 40% efficient metamorphic GaInP∕GaInAs∕Ge multijunction solar cells. Appl Phys Lett. 30 avr 2007;90(18):183516.Scappucci G, Kloeffel C, Zwanenburg FA, Loss D, Myronov M, Zhang JJ, et al. The germanium quantum information route. Nat Rev Mater. oct 2021;6(10):926-43.Abadie K, Fournel F, Morales C, Vignoud L, Colona JP, Widiez J. Manufacturing of Optimized Ge Substrates Using a Covalent Bonding Process. ECS Meet Abstr. 23 nov 2020;MA2020-02(22):1623.Takagi H, Kikuchi K, Maeda R, Chung TR, Suga T. Surface activated bonding of silicon wafers at room temperature. Appl Phys Lett. 15 avr 1996;68(16):2222-4.Rebhan B, Vanpaemel J, Dragoi V. 200 mm Ge Wafer Production for Oxide-Free Si-Ge Direct Wafer Bonding. ECS Trans. 8 sept 2020;98(4):87-100.Chao YL, Tong QY, Gösele UM. Thermomechanical stress in silicon on quartz wafer bonding and Smart Cut® process. MRS Proc. 2001;681:I5.10. [1] Trademark from S.O.I.T.E.C. .S.A. Figure 1

Electrically Tunable Ge/Si VIS-Swir Photodetector

Ge-on-Si photodiodes have been firstly reported more than twenty years ago opening the way for the integration of IR photodetectors on Si. A tremendous development has been done, moving from vertically illuminated, stand-alone devices, to waveguide integrated arrays of photodetectors and CMOS integrated imagers. Usually, the Ge epilayer act as the absorbing material for the NIR radiation, while Si acts only as a substrate. Here we report on a dual-band Ge-on-Si photodetector where light detection can take place both within the Ge epilayer and the underlying Si substrate: the device responsivity can thus be tuned from the VIS to the SWIR spectral range by means of an external bias. Therefore, the presented device can be implemented as a VIR-SWIR CMOS compatible imager.Two photodiodes in a back-to-back configuration are formed by p-doping the back side of a high resistivity Si wafer and by epitaxially growing a p-i-n heterojunction Ge-on-Si layer on the front side (Fig.1a)). An external bias can be applied to the whole layer stack by means of ohmic contacts formed on the top Ge layer and on the wafer backside (Fig.1b)). When a positive bias is applied between the top and bottom contact, the Ge diode is forward biased while the Si diode is reversed biased. In such a configuration the photocurrent generated within the Si substrate by back illuminating the device, will flow through the external circuit and be detected. By reversing the bias polarity, still maintaining a backside illumination, the photocurrent will be generated within the Ge epilayer: in this way it is possible to tune the device responsivity simply by controlling the external bias. A TCAD model has been set up to optimize doping levels, in particular that of the Si substrate, determining the most effective position the p-n junction within the Si photodiode and investigating the role played by substrate thickness[1].According with the simulation outcome, a p-type layer has been formed on the backside of an intrinsic Si wafer by spin-on-dopant obtaining a boron-doped layer with an average concentration of 2×1019cm-3 and a thickness of ≈300nm. The epitaxial growth has been performed by low-energy plasma-enhanced chemical vapor deposition (LEPECVD).Firstly, a 200nm thick phosphorous-doped Si layer has been deposited at 760°C followed by 3 µm thick nominally undoped Ge, grown at 500°C. Six thermal annealing cycles between 600-780°C have been performed in-situ to reduce the threading dislocation density. As a final step 150nm of boron-doped Ge have been deposited.Ge mesas with dimensions ranging between 100-500µm have been realized by standard UV-lithography and dry etching on the Ge-on-Si epitaxial layer. The mesas have been etched down to the intrinsic Si surface to electrically isolate the different devices on the same chip. The top ohmic contacts have been realized by e-beam deposition of a Ti/Al metal stack and lift-off. Different bottom ohmic contact have been tested both by depositing two rectangular stripes of Ti/Au or by depositing a transparent ITO layer on the backside of the chip.Optical characterization was performed by means of a lamp-monochromator set-up. The VIS/SWIR bias dependent dual-band operation of the device is demonstrated in Fig.1c), where the spectral responsivity is shown for two different applied voltages. The peak responsivities are 0.41A/W and 0.63A/W at 960nm and 1520nm, respectively. The specific detectivity D* of the device has been found to be 7·1011cmHz1/2/W and 2·1010cmHz1/2/W in the VIS and NIR, respectively[2].VIS-SWIR single-pixel imaging was performed by mounting the chip on a rastering system comprising a three-axis stage. In this way the pixel can scan the image plane behind a piano-convex lens. Two images, one in the VIS and one in the SWIR, can be obtained by repeating the scanning and changing the polarity of the applied bias at the device Fig.4d). A coloured VIS image has been obtained by repeating the measurements three times with three different optical bandpass filters (450nm, 550nm and 650nm) resulting in three images with R, G, and B components, which have been combined to obtain the final VIS image.In conclusion, we have designed and fabricated a voltage-tunable dual-band photodetector operating in the VIS and SWIR range. The device is based on a couple of p-i-n photodiodes connected back-to-back formed within a Ge-on-Si epitaxial structure. The device architecture enables to electronically select the shorter (400-1100nm) or longer (1000-1600nm) wavelength range with a relatively low applied voltage. VIS-SWIR single-pixel imaging has been performed.[1] A.De Iacovo, et al., Journal of Lightwave Technology, 37(14), 3517(2019).[2] E.Talamas Simola, et al., Opt. Express 27, 8529-8539(2019). Figure 1

Stress Relaxation in SGOI Structure Obtained by Condensation

Years of work have been dedicated to the optimization of thickstrain-relaxed buffers. Thanks to the use of graded Ge content layersbeneath the constant composition layers on top, threadingdislocations densities around 105 cm-2 have been obtained. Recentlyan innovative phenomenon has been observed concerning SiGe-On-Insulator (SGOI) layer relaxation. We propose to use this approachto obtain fully relaxed SGOI layers without dislocations in industrialconditions on 300mm wafers. This new approach would enable usto fabricate relaxed SGOI layers which are uniform in composition.Such an innovation would be relevant for several applications suchas, for instance, the re-epitaxy of Si0.5Ge0.5 layers.

High Quality Ge Growth on Si (111) and Si (110) by Using Reduced Pressure Chemical Vapor Deposition

A method for high quality epitaxial growth of Ge on Si (111) and Si (110) is investigated by reduced pressure chemical vapor deposition. Two step Ge epitaxy (low temperature Ge seed and high temperature main Ge growth) with several cycles of annealing by interrupting the Ge growth (cyclic annealing) is performed. In the case of Ge seed layer growth below 350 °C for (111) and 400 °C for (110) orientation, huge surface roughening due to too high dislocation density is observed after the following annealing step. For both crystal orientations, a high crystallinity Ge seed layer is realized by combination of 450 °C growth with 800 °C annealing. Once the high-quality Ge seed layer is deposited, high crystal quality Ge can be grown at 600 °C on the seed layer for both crystal orientations. For the 5 µm thick Ge layer deposited with the cyclic annealing process at 800 °C, a Si diffusion length of ~400 nm from the interface, RMS roughness below 0.5 nm and threading dislocation density of 5×106 cm-2 are achieved for both (111) and (110) substrates.

Reduced Dislocation of GaAs Layer Grown on Ge-Buffered Si (001) Substrate Using Dislocation Filter Layers for an O-Band InAs/GaAs Quantum Dot Narrow-Ridge Laser.

The development of the low dislocation density of the Si-based GaAs buffer is considered the key technical route for realizing InAs/GaAs quantum dot lasers for photonic integrated circuits. To prepare the high-quality GaAs layer on the Si substrate, we employed an engineered Ge-buffer on Si, used thermal cycle annealing, and introduced filtering layers, e.g., strained-layer superlattices, to control/reduce the threading dislocation density in the active part of the laser. In this way, a low defect density of 2.9 × 107 cm−2 could be achieved in the GaAs layer with a surface roughness of 1.01 nm. Transmission electron microscopy has been applied to study the effect of cycling, annealing, and filtering layers for blocking or bending threading-dislocation into the InAs QDs active region of the laser. In addition, the dependence of optical properties of InAs QDs on the growth temperature was also investigated. The results show that a density of 3.4 × 1010 InAs quantum dots could be grown at 450 °C, and the photoluminescence exhibits emission wavelengths of 1274 nm with a fullwidth at half-maximum (FWHM) equal to 32 nm at room temperature. The laser structure demonstrates a peak at 1.27 μm with an FWHM equal to 2.6 nm under a continuous-wave operation with a threshold current density of ∼158 A/cm2 for a 4-μm narrow-ridge width InAs QD device. This work, therefore, paves the path for a monolithic solution for photonic integrated circuits when III−V light sources (which is required for Si photonics) are grown on a Ge-platform (engineered Ge-buffer on Si) for the integration of the CMOS part with other photonic devices on the same chip in near future.