Third-order Intercept Research Articles

A 2–36 GHz CMOS LNA with π-Network-Based wideband interstage matching technique for software-defined radio systems

With the advance in wireless communication, next-generation software-defined radio (SDR) systems require transceivers to operate in both sub-6GHz and millimeter-wave (mmWave) band and support multiple standards. However, bridging sub-6GHz frequencies with millimeter-wave bands exceeding 30 GHz remains a challenge for conventional wideband LNAs. To surmount this, a 2–36 GHz CMOS low-noise amplifier (LNA) designed for SDR systems is introduced in this paper. An innovative wideband input matching network capable of spanning both frequency domains is proposed. The methodology effectively mitigates the impact of vast parasitic capacitances, achieving wideband input matching against Electrostatic Discharge (ESD) and on-chip decoupling capacitor parasitic. In addition, a π-network-based wideband interstage matching technique is adopted to extend bandwidth of gain. A tri-stage prototype of the proposed LNA, designed using a 40-nm CMOS process, is designed to validate our design strategies. The post-simulation outcomes reveal a peak gain of 14 dB with a -3dB bandwidth ranging from 2 to 36 GHz, equating to a fractional bandwidth of 178 %. The Noise Figure (NF) is commendably uniform across the frequency spectrum, stabilizing at 5 dB. Furthermore, the third-order input intercept point (IIP3) is −4.2dBm to -3dBm across the bandwidth. The performance is achieved with a power of 19.4 mW and within a core area of 0.1 mm2.

Characterizing third-order intermodulation distortion of photodetectors based on de-coupling and de-embedding modulation distortion of modulators

A novel, to the best of our knowledge, electro-optical modulation method is proposed for measuring third-order intermodulation distortion of photodetectors (PDs) based on de-coupling and de-embedding modulation distortion of modulators. The method utilizes dual parallel intensity modulation to generate electro-optical stimulus signals with fast and fine sweeping capability, and it eliminates the nonlinear impact of modulators by using low-frequency bias swing, allowing a direct extraction of the third-order output intercept point (OIP3) of PD from the combined nonlinear response contributed by both the modulators and the PD. The OIP3 of PD is frequency-swept measured with our method and compared to those with the conventional method to check for consistency. The proposed method enables a modulator-distortion-free, fast, and fine sweeping measurement of PDs using a simple system.

Investigating the effect of scaling and temperature on the performance of improved junctionless nanowire FET through simulation analysis

An Improved Junctionless Nanowire Field Effect Transistor (I-JL-NWFET) device is proposed in this paper to address the limitations of conventional JL-NWFET. This research paper initially, comprehensively analyzes the impact of channel length (L) and channel thickness (t si ) scaling on the electrical, analog/RF, and linearity performance of I-JL-NWFET and JL-NWFET. The results suggest that the specific design features in I-JL-NWFET contribute to a more robust and less sensitive response to variations in scaling compared to its counterpart, JL-NWFET. Furthermore, an exploration into the impact of temperature on the electrical, analog/RF, and linearity performance is also conducted for both I-JL-NWFET and JL-NWFET. The electrical performance of I-JL-NWFET showcases a significantly reduced temperature sensitivity in parameters like drain current (I D ), Subthreshold Slope (SS) and Drain Induced Barrier Lowering (DIBL) compared to JL-NWFET. Subsequently, analyzing the analog/RF performance in the context of parameters such as transconductance (g m ), Transconductance Gain Factor (TGF), output conductance (g d ), early voltage (V EA ), total gate capacitance (C GG ), and cut-off frequency (f T ) under temperature variation, a lower degree of variability in I-JL-NWFET is observed compared to JL-NWFET. Furthermore, the linearity performance of I-JL-NWFET, assessed through parameters such as second and third-order transconductance (g m2 , g m3 ), second and third-order input voltage intercept points (VIP2, VIP3), and third-order intermodulation distortion (IIP3 and IMD3) is improved at the higher temperature than that of JL-NWFET.

Two gm/ID design approaches for high-performance dual-resistive feedback noise-cancelling LNA

ABSTRACT In this article, a self-bias MOSFET-based dual-resistive feedback low-noise amplifier (LNA) is investigated. A detailed mathematical analysis of the addressed amplifier has been carried out using the return ratio-based feedback analysis technique. Furthermore, the LNAs have been simulated via Cadence using the TSMC 65 nm PDK. Two g m / I D strategies are described to handle the performance trade-offs for enhancing gain, noise figure (NF) and power consumption. The two strategies are conceptually similar to one another, with the selection of the transconductance efficiency being the only difference. While the first technique uses a transconductance efficiency to achieve the lowest power consumption while keeping an acceptable NF, the second strategy uses a particular transconductance efficiency for flawless noise cancelling without consideration for reduced power consumption. According to simulation results, the first recommended LNA has a voltage gain of 12 dB over a 3 dB bandwidth of 0.5–10 GHz, a minimal NF of 1.7 dB @ 7.014 GHz, a maximum NF of 1.932 dB @ 0.5 GHz, consumes 12.42 mW from a low supply voltage of 1.2 V and achieved a third-order intercept of −2.34 dBm @ 1 GHz. The simulation results of the second recommended LNA also show that it can operate with a low supply voltage of 1.2 V and still achieve a minimum NF of 0.978 dB @ 2.729 GHz, a maximum NF of 1.048 dB @ 6 GHz, II P 3 of 1.34 dBm and a voltage gain of 13 dB over a 3 dB bandwidth of 0.5–6 GHz with a consuming power of 25 mW.

A Pseudo-Differential LNA with Noise Improvement Techniques for Concurrent Multi-Band GNSS Applications

A low-noise amplifier (LNA) design with the operation of concurrent dual-band for Global Navigation Satellite System (GNSS) receivers with single channel is presented in this work. This LNA structure has an inductively degenerated cascode architecture and is pseudo-differential, operating at two frequencies simultaneously (1.2 GHz and 1.57 GHz). Two noise reduction/cancellation techniques, using load capacitor and feedforward path, respectively, are proposed resulting in an excellent improvement in the noise figure (NF). The input matching circuit uses both series and parallel resonant components to enable concurrency. The adopted pseudo-differential structure results in input balun elimination. Inductively degenerated cascode topology provides both input impedance and optimum noise impedance matching. The soundness of the proposed approach has been demonstrated in a 0.18-µm CMOS technology by TSMC. Simulation results show that at 1.2 GHz and 1.57 GHz the LNA achieves −13 dB and −11 dB of input matching, 24.6 dB and 24.7 dB of gain, 1.47 dB and 1.43 dB of NF, respectively. The input-referred 1-dB compression point (IP1dB) is around −16 dBm, while the input-referred third-order intercept point (IIP3) achieves −2.2 dBm at 1.2 GHz and −0.6 dBm at 1.57 GHz. The LNA draws about 13 mA from a 1.8-V supply voltage.

A novel programmable gain control low noise amplifier (PGCLNA) design for automatic gain control loop in BLE applications

Bluetooth low energy (BLE) is a widely used short-range communication protocol and BLE receivers frequently encounter transient high-power RF (radio frequency) signals from antennas, leading to receiver saturation. To address this issue, this work proposes a 2.4 GHz programmable gain control low-noise amplifier (PGCLNA), which is a key element in an automatic gain control (AGC) system for BLE receiver applications. The proposed PGCLNA achieves discrete levels of gain using the g m -boosting technique by splitting the negative feedback. The proposed circuit is simulated in UMC 180 nm technology and the maximum gain achieved is 41.4 dB, with a step decrease of 15 dB in discrete levels. The gain variations do not degrade the performance of S11, which is always less than -16 dB. The noise figure (NF) is always minimum of 5.5 dB and in high gain mode, the minimum value of NF is 1.82 dB. The third-order intercept point (IIP3) is −7.621 dBm in the best circumstances and always remains above −10.69 dBm. These results are achieved by utilising 5.4 mW power at 1.8 V of supply voltage. The circuit occupies an area of 732 μm × 771 μm. The proposed PGCLNA design offers a solution to accommodate a wide range of input signals in BLE receivers, excellent gain control, low noise and robust performance characteristics, making it an essential component in an AGC system for BLE receiver applications.

High linearity AlGaN/GaN HEMTs with Au-free Ti/Al/Ni/Ti ohmic contacts for Ka-band applications

In this study, AlGaN/GaN HEMTs with Au-free Ti/Al/Ni/Ti ohmic contacts were fabricated. The device presents a contact resistance (R c) of 0.64 Ω·mm and high linearity characteristics. The two-tone measurement at 28 GHz shows that the 2 × 50 μm device exhibits an excellent third-order intercept point (OIP3) value of 41.64 dBm at V DS = 28 V, and an OIP3/P DC of 24.2. An OIP3 of 46.59 dBm was achieved when the device’s gate width was increased to 8 × 50 μm at V DS = 48 V. These results demonstrate that AlGaN/GaN HEMTs with Ti/Al/Ni/Ti ohmic contacts have potential for Ka-band applications.

AI-DRIVEN TRANSFORMER NETWORKS IN SHARED SPECTRUM FOR ENHANCED SIGNAL PROCESSING FOR NONLINEAR RECEIVERS

Communication systems face challenges from high-power adjacent channel signals, or blockers, inducing nonlinear behavior in RF front ends. Ensuring robust performance in the presence of blockers is crucial for IoT and other spectrum-consuming devices coexisting with advanced transceivers. This paper proposes a flexible, data-driven solution using a Deep Belief Network (DBN) to mitigate third-order intermodulation distortion (IMD) during demodulation. Numerical evaluations of AI-enhanced receivers employing DBN as an IMD canceler and demodulator show significant improvements in bit error rate (BER) performance. The effectiveness of DBN varies with RF front end characteristics, notably the third-order intercept point (IP3).

RF linearity and improved transconductance of ScAlN/GaN HEMT with novel inverse L-shaped gate structure

In this study, we investigate the enhancement of effective transconductance and gain linearity in submicrometer gate AlGaN-barrier-based transistors utilizing ScAlN/GaN coupling-channel structures. A novel asymmetric gate design, incorporating an AlGaN cap on ScAlN/GaN HEMT, is proposed. This configuration demonstrates a flat transconductance profile and significantly reduced transconductance derivative, thereby improving the linearity of GaN-based transistors. For transistors with a gate length of 0.5 μm, both the current gain cut-off frequency and power gain cut-off frequency are measured at 53.52 GHz and 72.98 GHz, respectively. These values represent a more than threefold increase from the corresponding frequencies of conventional devices. Moreover, the theoretical Output Third-Order Intercept value of the proposed structure has increased by 7.5 dBm compared to conventional HEMTs. This superior linear performance can be attributed to the combined effect of AlGaN cap layer and air cavity. Furthermore, the introduction of the ScAlN layer results in a substantial impact, including a decrease in electron concentration from 4.96 × 1019/cm3 to 1.98 × 1019/cm3 and an increase in electron velocity from 4.5 × 107 to 7.6 × 108 cm/s. These findings underscore the potential of the proposed device for high-frequency applications requiring superior linearity.

A 3.2-3.8 GHz low-noise amplifier for 5G/6G satellite-cellular convergence applications

The rapid evolution of wireless communication systems towards 5G standards has imposed stringent requirements on the performance of radio frequency front-end components. Among these, the Low-Noise Amplifier (LNA) plays a pivotal role in determining the overall noise figure and sensitivity of the receiver chain. This paper presents a comprehensive design and analysis of a 3.2-3.8 GHz LNA tailored for 5G applications, employing a 0.3 μmm gate length Gallium Arsenide (GaAs) pseudomorphic high electron transistor (pHEMT) technology process. The proposed LNA design focuses on achieving a low noise figure (NF), high gain, and robust linearity to accommodate the dense signal environment and wide bandwidth of 5G networks. The design leverages advanced matching networks and feedback topologies to enhance stability and reduce the noise contribution from the active devices. Simulation results predict a noise figure of 1.3-1.4 dB, a gain of 20-21 dB across the band of interest, and an input-referred third-order intercept point (IIP3) of 18 dBm. The LNA demonstrates excellent performance in a 5G testbed, showing a significant improvement in the signal-to-noise ratio and the potential to enhance 5G receiver sensitivity. The research substantiates the LNA’s viability for integration into 5G base stations and user equipment, underscoring its potential to contribute to the efficient and reliable operation of next-generation wireless networks. This LNA can be used for 5G New Release (NR) band of n77 and n78 (3.5-3.7 GHz)

Mathematical modeling of microwave channels of a semi-active radar homing head

Objectives. Radar homing heads of guided missiles form a large group of radars which differ from other radars due to their specific purpose. The advantages of a semi-active radar homing head (SARH) include the ability to have a powerful irradiator at the command post and, as a result, a powerful reflected signal from the target. This results in an increase in the range of its detection and guidance. The absence of an emitter simplifies the missile’s onboard control equipment, reduces its weight and dimensions, thereby improving its maneuverability and increasing the guidance accuracy, resulting in the greatest distribution of this type of SARH. However, in order to determine the exact Doppler shift of the target signal as part of SARH, a reference signal with a frequency coinciding with the illumination transmitter signal must be supplied to the receiving path. This study aims to synthesize and analyze the SARH receiver circuit with improved accuracy characteristics.Methods. The following methods are used: statistical radio engineering; optimal signal reception theories; and computer modeling in CAD AWR Design Environment.Results. A mathematical model of the SARH receiver was obtained and analyzed. The proposed receiver model allows the spectral characteristics of signals to be calculated at any point of the microwave paths, as well as signal characteristics at the input of the head channel, at the output of the first conversion mixer, at the output of the first intermediate frequency selector, and at the output of the receiving path. The calculated values of the main characteristics of high-frequency channels are also given.Conclusions. The resulting model allows the frequency dependencies of main parameters of the receiving path, such as the gain factor, noise factor, decibel compression points, and third-order intermodulation intercept points to be estimated. The values obtained during the simulation are maximally close to existing systems, since the models of real-life and mass-used microcircuits thu created are used as the main elements when designing high- frequency paths. The model can be used to study methods of improving technical indicators, as well as to develop new principles and schemes for developing radioelectronic complexes, for example, when designing a receiving path using advanced radio photonics.

A Broadband Millimeter-Wave 5G Low Noise Amplifier Design in 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS

This paper presents a broadband millimeter-wave (mm-Wave) low noise amplifier (LNA) designed in a 22 nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology. Electromagnetic (EM) simulations suggest that the LNA has a 3-dB bandwidth (BW) from 17.8 to 42.4 GHz and a fractional bandwidth (FBW) of 81.7%, covering the key frequency bands within the mm-Wave 5G FR2 band, with its noise figure (NF) ranging from 2.9 to 4.9 dB, and its input-referred 1-dB compression point (IP1dB) of −17.9 dBm and input-referred third-order intercept point (IIP3) of −8.5 dBm at 28 GHz with 15.8 mW DC power consumption (PDC). Using the FOM (figure-of-merit) developed for broadband LNAs (FOM = 20 × log((Gain[V/V] × S21-3 dB-BW [GHz])/(PDC [mW] × (F-1)))), this LNA achieves a competitive FOM (FOM = 18.9) among reported state-of-the-art mm-Wave LNAs in the literature.

Robust Ku-Band GaN Low-Noise Amplifier MMIC

This paper employs the 0.2 μm ETRI GaN HEMT process on SiC to develop a Ku-band GaN low-noise amplifier monolithic microwave integrated circuit (MMIC) characterized by high-input power robustness for radar transceiver modules. A source degeneration inductor is employed to obtain the proposed amplifier’s stable operation and the compromised impedance trajectory of the maximum available gain and minimum noise figure. The analysis results show simultaneous gain and noise impedance matching, achieved using only a small number of passive elements. Furthermore, the proposed low-noise amplifier MMIC secures a linear gain of 21.3−22.6 dB, an input return loss of 19.6−21.4 dB, and a noise figure of 1.7−1.8 dB in the 15–16 GHz frequency range. It also exhibits an input 1 dB compression point of 0.4−1.5 dBm in the single-tone power test, and an input third-order intercept point of 5.8−10.1 dBm within the 15−16 GHz frequency range in the two-tone intermodulation distortion test.

A 22 nm CMOS 2.4 GHz 40.91 dB voltage gain RX front-end design

This briefing introduces a receiver (RX) front-end integrated with a virtual switch-based transmit/receive switch (TRSW) and a reconfigurable capacitor cross-coupled low noise amplifier (LNA) that employs the gain control scheme of direct shunt. Simulation and testing results indicate that the TRSW has an insertion loss of 0.2 dB and an isolation of 30 dB. The LNA achieves a maximum voltage gain of 40.91 dB or a power gain of 31.91 dB, a minimum S11 of −18.5 dB, and an input third-order intercept point of −22 dBm. The LNA consumes 2 mA from a 0.9 V power supply and has a minimum NF of 2.97 dB.

A 28 GHz Highly Linear Up-Conversion Mixer for 5G Cellular Communications

In this paper, we present a highly linear direct in-phase/quadrature (I/Q) up-conversion mixer for 5G millimeter-wave applications. To enhance the linearity of the mixer, we propose a complementary derivative superposition technique with pre-distortion. The proposed up-conversion mixer consists of a quadrature generator, LO buffer amplifiers, and an I/Q up-conversion mixer core and achieves an output third-order intercept point of 15.7 dBm and an output 1 dB compression point of 2 dBm at 27.6 GHz, while it consumes 15 mW at a supply voltage of 1 V. The conversion gain is 11.4 dB and the LO leakage and image rejection ratio are −56 dBc and 61 dB, respectively, in the measurement. The proposed I/Q up-conversion mixer is suitable for 5G cellular communication systems.

On Minimizing Charge Injection Error Using Multi-Dummy Switches With Enhanced Linearity

The paper proposes an ameliorated methodology to minimize the effect of charge injection over a wide input common-mode range. Instead of a conventional single dummy switch compensation [1], the multi-dummy switches are proposed and employed to eradicate the injected charge on to the sampling capacitor. A detailed methodology is presented to compensate the charge injection in a MOS switch. The closed-form equations are derived mathematically to substantiate the proposed technique. For the proof-of-concept, a track-and-hold (T/H) stage has been simulated in 0.18μm CMOS technology with the proposed technique for a 10-bit resolution. The proposed technique based T/H stage exhibits the spurious free dynamic range (SFDR) of 62.6 dB, effective number of bits (ENOB) of 9.36, peak input-referred third-order intercept point (IIP3) of 13.02 dBm and an input-referred 1 dB compression point (P1dB) of 3.8 dBm at 1.074 MHz input frequency, sampled at 100 MSa/s. The performance of the proposed method is compared with the existing single dummy switch compensation method where our technique shows 88.8% compensation in minimizing the charge injection error and 272% improvement in dynamic linearity. Moreover, the presented technique quantifies 9× improvement in mean percentage error (MPE) when simulated across the various process corners and rail-to-rail input common-mode voltage.

Third order intermodulation and third order intercept in a directly modulated Fabry–Perot laser diode

Abstract This paper presents measurement of third order intermodulation distortion and third order intercept (TOI) in a Fabry–Perot semiconductor laser lasing at 1550.3 nm when the laser is biharmonically bias-current modulated. Keeping the modulation current of one signal fixed, the third order intermodulation power at two different frequencies has been found to increase with the increase in second signal modulation power. There is an eventual crossover or tendency to crossover in the intermodulation characteristics when the modulation current amplitudes of the channels assume the same value. The TOI has been experimentally measured. The intermodulation power appearing at two different frequencies along with their signal power dependence and measurement of TOI constitute the outcome of this paper. The typical value of spurious-free dynamic range of the modulation scheme is 70 dB.

A Folded Cascode CMOS Low Noise Amplifier with Transformer Feedback

This study proposes a folded cascode CMOS low noise amplifier (LNA) with transformer feedback, implemented using a 0.13-μm CMOS process for wireless local area network front-end module applications. Compared to a conventional cascode inductive source degeneration LNA (ISDLNA), the folded cascode ISDLNA significantly improved the input-referred third-order intercept point (IIP3) as well as the 1-dB compression point (P1dB) by ensuring a large voltage headroom. Furthermore, the designed LNA also achieved a low noise figure (NF), while also saving the silicon area by magnetically coupling the source and folding inductors. When tested experimentally, the proposed LNA showed an S21 of 11.0 dB and an NF of 2.6 dB, while achieving an <i>S</i><sub>11</sub> of -7 dB at the operating frequency of 2.4 GHz. The measured input P1dB and IIP3 were -5.6 dBm and +2.5 dBm, respectively. The power dissipation was 9.6 mW from a 1.2-V supply voltage.

Compact K-Band Current Mode Tunable Active Only Bandpass Filter Using 32 nm CNTFET-Based MOCCCII

A low-power and compact carbon nanotube field-effect transistor (CNTFET)-based [Formula: see text]-band electronically tunable band-pass filter (BPF) is presented. The filter is designed using second-generation multiple-output current-controlled current conveyor (MOCCCII). The presented active only current-mode BPF employs three MOCCCIIs and two CNTFETs as capacitors. This BPF can be tuned by varying the parasitic resistance of MOCCCIIs via the control current. The designed current-mode tunable BPF is simulated in an advanced design system (ADS) using the Stanford CNTFET model with the extension of noise and manufacturing process variation. The filter achieves a 21–23 GHz tuning frequency range, with a minimum noise figure of about 11.09 dB. The 1-dB compression point and input-referenced third-order intercept point are −19.28 and −8.4 dBm, respectively. This compact filter consumes only 145.7 [Formula: see text] W power at ± 0.5 V supply voltage at room temperature. The temperature analysis shows good thermal stability. The Monte Carlo analysis demonstrates the good process variation stability of the filter. The suggested BPF can be thought of as the first fully active BPF that is a candidate for [Formula: see text]-band communication applications with future advances in the fabrication process for CNTFET.

An 18–28 GHz dual-mode down-converter IC for 5G applications

Emerging spectrum trends require a higher integration of 5G New Radio Frequency Range 1 (FR1) and Frequency Range 2 (FR2) bands to enhance the availability of spectrum and spectrum-sharing opportunities. To enable the reception of both FR1 and FR2 bands in a seamless hardware entity, we propose combining homodyne and heterodyne architectures. This necessitates the incorporation of a down-converter module that transfers the incoming signals from FR2 bands down to FR1, ensuring compatibility with an FR1 direct-conversion receiver (DCR) for the final signal reception. The primary focus of this paper is the design and implementation of the required integrated down-converter. The module includes an integrated balun, a low-noise amplifier (LNA) with a bypass mode, a dual-mode mixer, and an intermediate frequency (IF) amplifier. The introduced bypass mode helps to further elevate the linearity performance compared to the nominal mode. The bypass mode is designed for joint communication and sensing operation to avoid the compression of the receiver. This work also incorporates a local oscillator (LO) signal distribution network with phase tuning elements using a mixed-signal approach. The circuit is implemented in a 22-nm CMOS process, and the active die area is 0.6 mm2\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ ext {mm}^\ ext {2}$$\\end{document}. The measurements demonstrate that the implemented chip can efficiently perform the required frequency conversion over a wide frequency range of 18–28 GHz. Conversion gain of 4.5–7.5 dB, noise figure of 15–19.7 dB, 1 dB compression point (IP1dB) of − 16 to − 10 dBm, and input third-order intercept point (IIP3) of − 5 to 0 dBm are achieved. The measured IP1 dB and IIP3 for the bypass mode are +0.5 to +4.5 dBm and +8.5 to +10 dBm, respectively.