Thin Wafer Handling Research Articles

Compatibility of Dielectric Passivation and Temporary Bonding Materials for Thin Wafer Handling in 3-D TSV Integration

The effects of temporary bonding processes on thin wafer handling were investigated. Backside dielectric curing process was found to be a critical process for the void formation in the thin wafer handling which was confirmed by scanning acoustic microscope and by thermo-gravimetric analyzer out-gassing analysis. The effects of voids on back-side wafer processes were discussed. Finally, 3-D through silicon via integration with thin wafer handling (50 μm in thickness) was demonstrated with selected dielectric passivation material and temporary bonding adhesives.

Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300 mm Multi-Project Wafer (MPW)

The feasibility of a 3D IC integration SiP has been demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) interposer with an RDL (redistribution layer) on both sides, IPD (integrated passive devices), and SS (stress sensors). This interposer is used to support (with microbumps) a stack of four memory chips with TSVs, one thermal chip with heater and one mechanical chip with SS, and is then overmolded on its top side for pick and place purposes. The interposer's bottom side is attached to an organic substrate (with ordinary lead-free solder bumps), which is lead-free solder-balled on a PCB (printed circuit board). Key enabling technologies such as TSV etching, chemical mechanical polishing (CMP), thin-wafer handling, thermal management, and microbumping, assembly, and reliability are highlighted.

Thin Wafer Handling of 300mm Wafer for 3D IC Integration

In this study, thin wafer handling of 300mm wafer for 3D IC Integration is investigated. Emphasis is placed on the determination of the effect of a dicing tape on thin-wafer handling of wafers with Cu-Au pads, Cu-Ni-Au UBM, and TSV interposer with RDL. Also, thin-wafer handling critical issues such as the chip/interposer wafer, carrier wafer, temporary bonding, thinning, backside process, de-bonding, and assembly are presented and their potential solutions are discussed. Finally, state-of-the-art of materials and equipments for thin-wafer handling are examined.

Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300mm Multi-Project Wafer (MPW)

The feasibility of a 3D IC integration SiP has been demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) interposer with RDL (redistribution layer) on both sides, IPD (integrated passive devices) and SS (stress sensors). This interposer is used to support (with microbumps) a stack of four memory chips with TSVs, one thermal chip with heater and one mechanical chip with SS, and then overmolded on its top side for pick and place purposes. The interposer’s bottom-side is attached to an organic substrate (with ordinary lead-free solder bumps), which is lead-free solder-balled on a PCB (printed circuit board). Key enabling technologies such as TSV etching, chemical mechanical polishing (CMP), thin-wafer handling, thermal management, and microbumping, assembly and reliability are highlighted.

Thin Wafer Handling Challenges and Emerging Solutions

Temporary bonding attaches substrates to a carrier so that after thinning to the desired thickness further backside fabrications steps can be conducted with "normal" process flows in standard semiconductor equipment. The selection of a suitable temporary adhesive is key to the success of thin wafer handling. The major requirements of temporary adhesives are related to its process flow, thermal stability, chemical resistance, and mechanical strength. The ideal thermal stability should allow high temperature processing up to 400C for dielectric deposition in high aspect ratio vias, polymer curing, solder reflow, metal sintering, permanent bonding or other high temperature processing. The adhesive must be resistant to the chemicals commonly used after wafer thinning. Mechanical strength is required to hold the thin wafer rigidly during processing, especially during permanent bonding applications otherwise the thinned wafer will flex and prevent bonding. The challenge arises in finding a simultaneous solution to these problems while allowing for the gentle release of the thinned substrate to its final, permanent substrate or package without yield loss or stress. This paper will highlight some of the more recent solutions for thin wafer handling that have emerged through technology innovation.

Using Permanent and Temporary Polyimide Adhesives in 3D-TSV Processing to Avoid Thin Wafer Handling

3D chip integration processes use thinned silicon wafers in conjunction with through silicon vias. Polyimide adhesives are evaluated for use as temporary and permanent adhesives to enable handling of thinned wafers and subsequent bonding into 3D stacks. These adhesives are found to have a combination of thermal and mechanical properties and processing capabilities required for 3D chip integration applications.

Using Permanent and Temporary Polyimide Adhesives in 3D-TSV Processing To Avoid Thin Wafer Handling

This paper will examine the combined use of both permanent and temporary high-temperature polyimide adhesives used to avoid thin wafer handling. While 3D-TSV technology can improve functionality and performance, adoption of this technology has been delayed by cracking as well as unwanted wafer bowing. This presentation shows means by which a photo-lithographic polyimide adhesive is used in a temporary bonding scheme to eliminate intermediate-stage thinned wafer handling.

A new approach for handling and transferring of thin semiconductor materials

Based on the fracture mechanics analysis of crack propagation, the phenomenon of subcritical crack growth was utilized for a controlled debonding of directly wafer-bonded interfaces. The approach allowed the well-defined separation of bonded wafers although the bond strength was high due to thermal annealing. The achieved splitting velocity depended on the wafer material, the wafer thickness ratio, the bonding process parameters, and the environmental conditions during cleaving. In combination with wafer bonding, the method can be used for a temporary stiffening and handling of thin and brittle wafers during fabrication, even if the wafers are exposed to high process temperatures. The approach can also be applied to fabricate micromechanical systems (MEMS).