Thin-film Silicon-on-insulator Research Articles

Silicon on insulator material by Wafer Bonding

Thermal bonding of oxidized silicon wafers is used to obtain high-quality silicon on insulator (SOI) starting material for electronics and sensor applications. An overview of the technology is followed by a detailed description of the bonding technique and the ensuing wafer thinning processes for making SOI of various film thicknesses. Bonded pairs of wafers can be reproducibly produced free of contact voids. Thick-film SOI is produced using a simple bond and grind/polish technique. Thin-film SOI, suitable for CMOS applications, is produced using the bond and etch back (BE-SOI) process. A comparison of selective etch-back chemistry with different etchstop fabrication techniques is presented. These methods produce inexpensive, low-defect SOI, for integrated circuit applications, using materials and equipment common to silicon integrated circuit process lines.

Thin-film SOI CMOS transistors with p/sup +/-polysilicon gates

A comparison is given of the use of p/sup +/-polysilicon and n/sup +/-polysilicon as the gate material for high-performance CMOS processes in fully depleted, thin SOI (silicon on insulator) films. Experimental devices on Simox substrates are compared with numerical simulations. It is found that n-channel transistors with p-poly gates require lower channel doping levels than their n-poly counterparts, leading to higher gains and easier control of the threshold voltage. The lower electric fields in the p-poly transistor also result in improved drain breakdown characteristics. Control of the subthreshold and punch-through characteristics of the p-poly device requires the use of very thin films when there is significant fixed positive charge at the interface with the buried oxide. >

Role of surface morphology in wafer bonding

The strain patterns detected by x-ray topography in wafers bonded for silicon-on-insulator (SOI) technology were found related to the flatness nonuniformity of the original wafers. Local stresses due to the bonding process are estimated to be about 1×108 dynes/cm2. The stress is reduced about 100 times for the thin (0.5 μm) SOI films. Most of the wafer deformation occurs during room temperature mating of the wafers. The deformation is purely elastic even at 1200 °C. The magnitude of the stress appears insignificant for complimentary metal-oxide-semiconductor devices performance.

SIMOX devices and circuits

The initial driving force for the CMOS silicon-on-insulator (SOI) technology development was the promise of improved circuit performance due to the reduced junction capacitance, latch-up free dielectric isolation, higher packing density and radiation hardness. Recent material improvements and successful LSI/VLSI circuit demonstrations have made SIMOX the leading SOI approach for CMOS circuits. The simplicity in the scaling of SIMOX integrated circuit (IC) processing and the recent demonstration that very thin film SOI MOSFETs offer significant performance improvement over bulk devices make SIMOX technology a viable alternative to the bulk CMOS scaling in the sub-half micrometer regime. This paper reviews the characteristics of the SOI devices, and the implementation of LSI/VLSI circuits on SIMOX substrates.

Characterization of bipolar snapback and breakdown voltage in thin-film SOI transistors by two-dimensional simulation

A two-dimensional finite-difference simulator for silicon-on-insulator (SOI) MOSFETs is presented. The simulator is derived from the MINIMOS4 simulator and incorporates additional features which permit the characterization of the bipolar snapback effect, which has been observed as a limiting feature in ultra-thin-film transistors. The snapback effect is illustrated as a hysteresis mechanism whereby, for a given bias condition, there are two different solutions to the semiconductor equations, depending on the starting condition. Examples of the application of the simulator to predict breakdown voltage in submicrometer devices are considered. Excellent agreement with measured values of breakdown voltage has been achieved for submicrometer n-channel transistors, both with and without the use of lightly doped drains. >

Temperature dependence of threshold voltage in thin-film SOI MOSFETs

A first-order model for the temperature dependence of threshold voltage in thin-film silicon-on-insulator (SOI) n-MOSFETs is described. The temperature dependence of the threshold voltage of thin-film SOI n-channel MOSFETs is analyzed. Threshold voltage variation with temperature is significantly smaller in thin-film (fully depleted) devices than in thick-film SOI and bulk devices. The threshold voltage is shown to be dependent on the depletion level of the device, i.e. whether it is fully depleted or not. There exists a critical temperature below which the device is fully depleted, and above which the device operates in the thick-film regime.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Numerical and charge sheet models for thin-film SOI MOSFETs

Numerical charge sheet models applicable for all bias conditions are presented for the channel currents of long-channel SOI MOSFETs. From a comparison of the two models it is shown that the charge sheet analytic model accurately predicts the channel currents from weak to strong inversion regions. The results include analytic expressions for the drift and diffusion current components of individual channel currents, the front-gate and back-gate interaction parameter, and an analytic correlation between the surface potentials of the front and back channels when there is coupling between the two gates under nonthermal equilibrium conditions. The effect of SOI (silicon on insulator) film thickness on the drain current was investigated under different bias conditions for the back gate, and it was found that thin films are beneficial from the point of increased drain currents if the back channel is in depletion or inversion. It is also shown that, in addition to the charge coupling effects, dynamic interaction between the channels exists if the static current in one of the channels saturates.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Submicrometer near-intrinsic thin-film SOI complementary MOSFETs

Two-dimensional numerical simulations indicate that a surface-potential bending greater than the Si-film Fermi potential is required to reach the threshold condition for the near-intrinsic thin-film SOI (silicon-on-insulator) MOSFETs. Additionally, both n- and p-type SOI films result in approximately the same device threshold voltage when in the near intrinsic state and fully depleted condition. The threshold voltages of these devices are mainly dependent on the work function of gate material. High-performance submicrometer near-intrinsic thin-film SOI complementary MOSFETs with balanced threshold voltages of about 0.4 V (negative for PMOSFETs) are achievable with proper selection of gate material and back-gate bias. For very thin (less than 100 nm) SOI films, drain-induced barrier lowering (DIBL) is not sufficient to cause degradation of the threshold voltage or punchthrough behavior in the submicrometer region. For relatively thick (greater than 100 nm) SOI films, DIBL becomes more pronounced but can be suppressed by a proper back-gate bias. The simulated front-gate linear transconductance remains nearly constant up to about 10/sup 15/ cm/sup -3/ and then falls off rapidly with increasing doping concentration because of mobility degradation. The subthreshold slope increases with decreasing drain voltage as a result of DIBL, but the increase is small for very thin SOI films.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-quality thin-film SOI technology using wafer bonding and selective polishing for VLSIs

The authors have developed a novel technique for obtaining bulk quality thin-film SOI (silicon-on-insulator) by wafer bonding and selective polishing. 625- mu m-thick 5-in.-diameter

Gate coupling and floating-body effects in thin-film SOI MOSFETs

Thin-film, silicon-on-insulator (SOI) MOSFETs exhibit bias-dependent suppression of the kink effect. For zero or positive back gate bias, the well known kink effect is suppressed but the threshold voltage depends strongly on back gate bias. For sufficiently negative back gate bias (as might be required for total-dose radiation-hard applications), the kink effect reemerges and the threshold voltage depends instead on the applied drain voltage.

Subthreshold slope of thin-film SOI MOSFET's

Silicon-on-insulator (SOI) n-channel transistors have been made in thin (90 nm) silicon films. Both modeling and experimental results show that excellent subthreshold slopes can be obtained (62 mV/ decade) when the silicon film thickness is smaller than the maximum depletion depth in the transistor channel. For comparison, the subthreshold slope of transistors made in thicker films is also reported.

Current-voltage characteristics of thin-film SOI MOSFET's in strong inversion

A simple analytic model for the steady-state current-voltage characteristics of strongly inverted silicon-on-insulator (SOI) MOSFET's is developed. The model, simplified by a key approximation that the inversion charge density is described well by a linear function of the Surface potential, clearly shows the dependence of the drain current on the device parameters and on the terminal voltages, including the back-gate (substrate) bias. The analysis is supported by measurements of current-voltage characteristics of thin-film (laser-recrystallized) SOI MOSFET's. The dependence of carrier mobility on the terminal voltages, especially the back-gate bias, is analyzed and shown to underlie discrepancies between the theoretical (constant mobility) and experimental results at high gate voltages. The mobility dependence on the back-gate bias enhances the strong influence of the back gate on the drain current, especially when the device is saturated.

Linear-region conductance of thin-film SOI MOSFET's with grain boundaries

The linear-region conductance of silicon-on-insulator (SOI) MOSFET's is modeled by properly combining theoretical descriptions of the effects of grain boundaries in the channel region and of charge coupling between the front and back gates. The model is supported by measurements of thin-film SOI MOSFET's with and without grain boundaries. The theoretical-experimental analysis clearly distinguishes the charge-coupling effect from the grain-boundary effect, both of which can be beneficial to the MOSFET performance, and shows that the effects are not simply superimposed.