Silicon-on-insulator Thickness Research Articles

Demonstration of VGAA-TFETs using InAs/Si Heterojunction on SOI substrate

Introduction Miniaturization of field-effect transistors (FETs) have serious issues in enhanced leakage current, short-channel effect, and power consumption. In this regard, the vertical gate all-around (VGAA) structure using the III-V compound semiconductor nanowires (NWs) is expected as alternative transistor to solve the problems in leakage current and short channel effect. There is still challenge in decreasing power consumption of the FET because the reduction in subthreshold slope (SS) has physical limitation in thermionic carrier transport (SS = 60 mV/dec). Tunnel FETs (TFETs) can lower the SS less than the physical limitation in MOSFETs and are expected to be used as next-generation low-voltage switching devices. We have demonstrated vertical gate-all-around (VGAA) TFET using III-V/Si tunnel junction which was formed by the selective-area growth of III-V NWs on Si and achieved a steep SS characteristics and complementary operation [1]. These demonstrations should be expanded on silicon-on-insulator (SOI)(111) platforms toward circuit applications using the III-V/Si VGAA-TFETs. Here, selective-area growth of the InAs NWs on thin SOI(111) substrates and demonstrated InAs/Si VGAA-TFETs on SOI platforms.Experimental procedureFirst, a 35-nm-thick SiO2 film was formed on p-type SOI(111) by thermal oxidation. The SOI thickness was 600 nm. Periodical circular openings were formed using electron beam lithography and dry/wet etchings. Next, InAs NWs were grown by selective-area growth. Here, we used a pulse growth technique to orient NWs in the vertical <111>B direction on a nonpolar SOI substrate, making the substrate surface polar (111)B, and aligning vertical NWs [2]. Next, we fabricated VGAA-TFETs by using three-dimensional device process in previous reports [1]. First, Hf0.8Al0.2O were formed as gate oxides by atomic layer deposition (ALD). Next, 200 nm-thick tungsten (W) was deposited around the NW sidewalls as gate metal. After that source metal (Ti/Au) was evaporated 20 nm/50 nm on the substrate by EB vapor deposition. Next, benzocyclobutene (BCB) was used as isolation layer between gate and drain metals. Then drain metal (Ti/Pd/Au) was evaporated 20 nm/20 nm/50nm on the top of the NWs. Finally, the VGAA-TFETs were annealed at 350 - 400°C in order in N2 for ohmic contacts in the source and drain regions. VGAA-TFETs were measured after annealing for each temperature.ResultsThe growth results showed vertical InAs NWs were successfully integrated on the p-SOI(111) substrates. The grown InAs NWs have hexagonal pillar structures surrounded with {-110} vertical facets and (111) B planes. Each NWs were composed of axial Zn-pulse doped intrinsic/Si-doped n-type/Sn-pulse doped n+-type NW segments. The average height is inversely proportional to the square of the diameter. Therefore, as similar to the conventional selective growth of InAs NWs on Si(111), the surface diffusion process of In atoms was dominant for the NW growth on SOI(111) surface.Transfer characteristics of the fabricated VGAA-TFET after annealed at 350°C indicated the tunnel current in the InAs/Si tunnel junction was electrically modulated by gate bias. The minimum SS was 37 mV/dec at VDS = 0.50 V, which was less than the theoretical limitation of conventional MOSFETs.The on-state current was 21 nA/μm at drain and source (VDS) of 1.00 V. The off current was 6.5 fA/μm when VDS was 1.00 V. Also, the threshold voltage (VTH) was 0.55 V. Transconductance was 31 nS/μm at VDS = 0.50 V. The measured current and transconductance were normalized by the number of NWs and the gate outer perimeter.We also investigated anneal temperature dependence of the device performance. The increasing in anneal temperature slightly lowered the minimum SS from 37 mV/dec to 23 mV/dec. And the on-state current was increased with increasing the anneal temperature. However, nonlinearity in the output IDS – VDS curve was enhanced with increasing the anneal temperature. This was assumed to be formed Schottky contact on the source metal. At the higher anneal temperature above 380°C, Ti/Au source metal possibly formed silicide (TiSi2) layer at the Ti/p-SOI interface. Thus, the contact resistance was decreased by the silicidation, and the on-state current was increased. However, Schottky contact of Au/Si was partially formed through the silicidation layer due to the very thin Ti interlayer. One of the possible approaches was to increase the Ti thickness or to use Al or Cu as single layer film. Further improvement of the device performance will be discussed.[1] K.Tomioka et al., IEEE IEDM. Tech. Dig. (2020) 429-432[2] K.Tomioka et al., Nano Lett. 8(2008) 3475-3480

Design and reliability assessment of an ultra-thin body electrostatically doped bipolar transistor for mixed signal applications

Shrinking of the thickness of silicon on insulator (SOI) has been proposed as a potential solution for scaling down the physical base length of symmetric lateral electrostatically doped bipolar transistors. An ultra-thin body device that utilizes the full SOI thickness has been presented and the performance of the same is investigated in detail. The device features two distinct doping techniques: work function-induced electrostatic doping (WED) and bias-induced electrostatic doping (BED). The proposed design approach leads to significant improvements in gain and cut-off frequency compared to previously reported designs. The resulting devices exhibit peak current gain β values >1100, ft>500 GHz, fmax>1300 GHz. Moreover, these improved device performance matrices get translated into better performance of universal gates with low rise and fall time of ∼1.3 ns, and improved noise margin performance in static random access memory (SRAM) device of 0.43 and 0.41 for WED and BED based devices respectively. Furthermore, the study investigates the reliability of the device concerning breakdown voltage and its response to different temperature conditions. The findings reveal a decline in the β value for WED-based devices when subjected to temperatures exceeding 340 K. In contrast, BED-based devices demonstrate a comparatively smaller variation in β at temperatures above 340 K. These results show the potential of the proposed device for mixed-signal and digital circuit applications.

Ultra-High-Q Racetrack Resonators on Thick SOI Platform Through Hydrogen Annealing Smoothing

We implemented a hydrogen annealing based post-processing technique as a tool to improve the sidewall roughness of 3 μm thick silicon-on-insulator (SOI) waveguides and demonstrated ultra-high- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i> factors on racetrack resonators leveraging on the propagation loss reduction achieved through the smoothing process. The designed racetracks are based on a combination of rib waveguides and strip-waveguide-based Euler bends. We measured intrinsic quality factors of 14×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> for a racetrack with a footprint of ∼5.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 10.7×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> for a smaller racetrack with footprint of ∼1.48 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The estimated propagation loss for the rib waveguides was ∼2.7 dB/m, representing a ×3 reduction respect to the previously measured losses of 3 μm thick SOI rib waveguides treated with thermal oxidation smoothing. Overall, the post-processing technique allowed to significantly reduce the sidewall roughness without altering the geometry of the waveguides, unlike in sub-micron scale SOI platforms, making it an attractive solution for applications demanding ultra-low losses.

Electrical characterization of thin silicon-on-insulator films doped by means of phosphorus end-terminated polymers

Ex-situ doping of 30 nm thick silicon-on-insulator (SOI) substrates is performed by using polymers terminated with a doping containing moiety. Poly(methylmetachrylate) polymers with a P containing moiety are used to create a phosphorus δ-layer at the interface between the Si device layer and a 10 nm thick SiO2 capping layer deposited on the SOI sample by conventional e-beam evaporation. Drive-in of the P atoms is performed by annealing the samples in a rapid thermal processing (RTP) system at temperatures (TA) ranging from 900 to 1200 °C in N2 atmosphere. Annealing time is properly selected to inject a constant P dose of ∼ 1 × 1013 cm−2 into the SOI substrate, achieving a uniform dopant concentration throughout the entire Si device layer as verified by Time-of-Flight Secondary Ion Mass Spectroscopy (ToF-SIMS) measurements. Sample resistivity (ρ), carrier concentration (ne) and mobility (μ) are determined combining sheet resistance and Hall measurements in the van der Pauw configuration. An average activation rate above 95% is observed at room temperature in the samples annealed at 1000 °C for 100 s, suggesting complete activation of the injected dopants. The detection of phosphorus signal by EPR analysis confirms the extremely high effective concentration of dopants. Low temperature (5–300 K) electrical characterization of a 30 nm thick SOI sample (ne ∼ 2.7 × 1018 cm−3 at 300 K) indicates that the evolution of ρ, ne and μ values as a function of temperature are perfectly consistent, within the experimental error, with those reported for a P doped bulk Si.

T/R RF Switch with 150 ns Switching Time and over 100 dBc IMD for Wideband Mobile Applications in Thick Oxide SOI Process.

This paper presents a fast-switching Transmit/Receive (T/R) Single-Pole-Double-Throw (SPDT) Radio Frequency (RF) switch. Thorough analyses have been conducted to choose the optimum number of stacks, transistor sizes, gate and body voltages, to satisfy the required specifications. This switch applies six stacks of series and shunt transistors as big as 3.9 mm/160 nm and 0.75 mm/160 nm, respectively. A negative charge pump and a voltage booster generate the negative and boosted control voltages to improve the harmonics and to keep Inter-Modulation Distortion (IMD) performance of the switch over 100 dBc. A Low Drop-Out (LDO) regulator limits the boosted voltage in Absolute Maximum Rating (AMR) conditions and improves the switch performance for Process, Voltage and Temperature (PVT) variations. To reduce the size, a dense custom-made capacitor consisting of different types of capacitors has been presented where they have been placed over each other in layout considering the Design Rule Checks (DRC) and applied in negative charge pump, voltage booster and LDO. This switch has been fabricated and tested in a 90 nm Silicon-on-Insulator (SOI) process. The second and third IMD for all specified blockers remain over 100 dBc and the switching time as fast as 150 ns has been achieved. The Insertion Loss (IL) and isolation at 2.7 GHz are −0.17 dB and −33 dB, respectively. This design consumes 145 uA from supply voltage range of 1.65 V to 1.95 V and occupies 440 × 472 µm2 of die area.

(Invited) Monolithic Ge Integration on the 3 μm SOI Platform for 40 GHz Photodiodes

Silicon photonics offers the possibility to integrate a large number of photonic components on a small Si chip in a similar fashion as microelectronic circuits have been realized for many decades. This enables low power consumption, small footprint and low-cost mass production. Application areas for Si photonics reach from optical communication and computing to optical sensing and imaging. Monolithic germanium PIN detectors are one of the key components in photonic integrated circuits (PICs) and convert light into electrical signals. Germanium is the preferred material for photodetectors in silicon photonics as it absorbs light in the datacom and telecom wavelength range (1.2-1.7 μm) due to its small bandgap. Germanium is also tolerated in the IC-clean manufacturing lines, unlike many other potential semiconductor materials. Electron and hole mobilities in germanium are high, enabling high-bandwidth detectors. Challenges in Ge integration on silicon-on-insulator (SOI) wafers include unintentional oxidization and etching in many of the standard silicon technology processing steps, fast diffusion of n-type dopants in Ge and relatively large lattice mismatch between Ge and Si.High refractive index contrast between silicon (3.5) and silicon dioxide (1.5) is the key to achieve ultra-dense photonics integration. Most of the silicon photonics research is carried out using submicron-thick SOI waveguides and latest microelectronics fabrication technologies that involve (and require) very small wafer topography. In this paper, we present Ge photodiode integration on a 3 µm SOI platform with 3 µm thick Si waveguides. Those offer ultra-low propagation losses (~0.1 dB/cm), ultra-dense integration (μm-scale bends), small polarization dependency (down-to-zero birefringence) and ability to tolerate relatively high optical powers (>1W). One major limitation on the 3 µm SOI platform has been the lack of as fast modulators and photodetectors as those integrated on sub-µm SOI platforms. In this work, we monolithically integrated a fast horizontal PIN photodiode on the 3 µm SOI platform. The 3 dB cutoff frequency was 40 GHz and the responsivity was 1.0 A/W at -1 V bias and 1.55 µm wavelength. This high bandwidth indicates that the detector is limited by the transit time of the carriers over the i-region, rather than the junction capacitance. The electric field in the i-region at -1 V is sufficient to keep the carrier drift speed close to the maximum carriers velocity in Ge.The design of the 40 GHz PD included analytical calculations and numerical simulations. Physical dimensions of the detector were chosen so that they are compatible with the 3 µm SOI process flow and meet the bandwidth and responsivity targets. Germanium was selectively grown into cavities in the 3 µm SOI layer, leading to very low amount of stress-induced crystal defects. The Ge waveguide detector and the Si waveguides were patterned with a common hard mask to achieve self-alignment between them. The n- and p-contacts were directly made into Ge using Ti/Al metallization. The vertical sidewalls of the Ge detector were implanted in order to create a horizontal PIN structure. Due to high confinement of light into the 3 µm thick SOI and Ge waveguides, the 3 µm thick and 1 µm wide Ge detector could be made as short as 9 µm. This led to small junction capacitances. The electrical output pulse shape was not distorted by the slow diffusion current of electrons and holes because the incoming light does not enter the doped regions. The development of 40 GHz PDs was an important step in improving the feasibility of the 3 µm SOI platform in high-bandwidth applications. Figure 1

High coupling efficiency 2D metasurface integrated with strip waveguide in SOI for mid‐IR wavelengths

Two-dimensional (2D) metasurface integrated with strip waveguide in silicon-on-insulator (SOI) has been designed to achieve high coupling efficiency for 3.8 μm wavelength. The optimisation in period and radius has been achieved using 3D finite-difference time-domain (FDTD). The calculated coupling efficiency in the in-plane waveguide for the out-of-plane surface illumination is over 90% with a bandwidth of 1 μm. The design is consistent with the available lithography using 400 nm thick SOI for mid-IR applications. Finally, monolithic integration can be achieved using standard multi-project wafer run.

Transient Response of 0.18-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;${\mu}$ &lt;/tex-math&gt; &lt;/inline-formula&gt;m SOI MOSFETs and SRAM Bit-Cells to Heavy-Ion Irradiation for Variable SOI Film Thickness

In this paper, the effect of silicon-on-insulator (SOI) thickness scaling in fully and partially depleted SOI (FD-SOI and PD-SOI) devices is analyzed for their transient response to heavy-ion irradiation. We have analyzed radiation performance of FD-/PD-SOI MOSFETs and 6-T SRAM bit-cells, conforming to 0.18- $\mu \text{m}$ technology node, using calibrated 2-D TCAD simulations. We, for the first time, report here that while SRAMs designed with FD-SOI devices have superior hardness to heavy-ion radiation, they are also more sensitive to SOI film thickness than the SRAMs designed with PD-SOI devices. The slopes of the critical linear energy transfer (LETC) to SOI film thickness curves are +1000 and −950 000 $\text {MeV}\cdot \text {cm/mg}$ for PD-SOI and FD-SOI devices at 1.8V supply voltage ( ${V} _{\text {DD}}$ ), respectively. The negative slope for FD-SOI device indicates better radiation performance for thinner silicon films, while a positive slope in PD-SOI device indicates better radiation performance with thicker silicon films. We further investigated the effect of ambient temperature and supply voltage ( ${V} _{\text {DD}}$ ) on SOI thickness scaled FD-/PD-SOI devices. We show that increasing ${V} _{\text {DD}}$ results in increased generated charge due to the heavy-ion at transistor level, whereas LETC of the SRAM bit-cell improves with increasing ${V} _{\text {DD}}$ . We further highlight that the heavy-ion radiation response as a function of ambient temperature depends not only on the thickness of the SOI film but also on the LET of the impinging heavy-ion.

A Novel DRAM Cell Structure with Parasitic Storage Capacitance for SoCs on SoI Wafer in 65nm Planar MOS Technology

A novel 65nm Dynamic Random access memory (DRAM) cell, namely capacitor less RectFET based DRAM cell (CLRDC) is explored in silicon-on-insulator (SoI) wafer for embedded-DRAM (eDRAM) for system-on-chip (SoC), applications with Rectangular FET (RectFET) as its pass-transistor (PT). This CLRDC exploits its parasitic surround buried oxide capacitance (SBC) of SoI-wafer around RectFET (source) for realizing its ‘charge storage capacitance (Cs). For Cs=30fF (femtoFarad) target, it’s found to need an area factor of 4.3µm2 with 5nm thick SoI buried-oxide. This SoI wafer is explored to yield a capacitance density Cbuox=6.91 fF/µm2. The DC parameters of the PT are found to be very sensitive to process anneal temperature (Ta) and so are its DC characteristics too. A 2% increase in the Ta from a nominal 1000oC has resulted in an increase of 30% and 1.1% in the RectFET’s leakage (Idsat-off=I-off) and on-state (Idsat-on=I-on) currents respectively. The CLRDC cell transfer ratio T is also found to be a function of small signal frequency (f), Ta, and source/drain bias voltages Vs/Vd, respectively. And finally the retention characteristics of this CLRDC is again found to be a function of I-off and I-on currents of RectFET, when studied at RectFET’s (drain) supply voltage VDD=1.2V.

A Novel DRAM Cell Structure with Parasitic Storage Capacitance for SoCs on SoI Wafer in 65nm Planar MOS Technology

A novel 65nm Dynamic Random access memory (DRAM) cell, namely capacitor less RectFET based DRAM cell (CLRDC) is explored in silicon-on-insulator (SoI) wafer for embedded-DRAM (eDRAM) for system-on-chip (SoC), applications with Rectangular FET (RectFET) as its pass-transistor (PT). This CLRDC exploits its parasitic surround buried oxide capacitance (SBC) of SoI-wafer around RectFET (source) for realizing its ‘charge storage capacitance (Cs). For Cs=30fF (femtoFarad) target, it’s found to need an area factor of 4.3µm2 with 5nm thick SoI buried-oxide. This SoI wafer is explored to yield a capacitance density Cbuox=6.91 fF/µm2. The DC parameters of the PT are found to be very sensitive to process anneal temperature (Ta) and so are its DC characteristics too. A 2% increase in the Ta from a nominal 1000oC has resulted in an increase of 30% and 1.1% in the RectFET’s leakage (Idsat-off=I-off) and on-state (Idsat-on=I-on) currents respectively. The CLRDC cell transfer ratio T is also found to be a function of small signal frequency (f), Ta, and source/drain bias voltages Vs/Vd, respectively. And finally the retention characteristics of this CLRDC is again found to be a function of I-off and I-on currents of RectFET, when studied at RectFET’s (drain) supply voltage VDD=1.2V.

Hole Mobility Characteristics with Surface Roughness on Silicon-on-Insulator Substrate

Hole mobility characteristics were investigated with surface roughness and silicon-on-insulator (SOI) thickness variations to investigate the influence of surface roughness to mobility. The root mean square roughness varied between 0.16, 0.85 and 10.6 nm in 220, 100 and 40 nm thick SOI samples. Hole mobility was measured and analyzed as a function of effective field and temperature with the variations of surface roughness. The hole mobility, determined by transconductance, greatly decreased with the increase of effective field due to the increased surface roughness scattering in 40 nm thick SOI samples. On the other hand, phonon scattering was a dominant mechanism with the increase of temperature, irrespective of surface roughness and SOI thickness. The induced surface roughness of the devices increases the phonon scattering, thereby reducing the electron and hole mobility. The hole mobility decreases with the roughening of the samples, with the increase of temperature due to increased phonon scattering. Therefore, for enhanced mobility, surface scattering and phonon scattering should be controlled even in atomic scale roughened samples.

Hot-carrier-induced current capability degradation and optimization for lateral IGBT on thick SOI substrate

In this paper, the hot-carrier-induced current capability degradation of a 600 V lateral insulated gate bipolar transistor (LIGBT) on thick silicon on insulator (SOI) substrate is investigated. Our experiments found that, for the SOI-LIGBT, the worst stress condition is the maximum gate voltage (Vgmax) condition and the current degradation is dominated by the damages in the channel region under the Vgmax stress condition. However, further analyses show that the influence of channel region damages on the collector current degradation increases with the increase of measured collector voltage and is maximum in the current saturation region. Therefore, in our opinion, the hot-carrier-induced current capability degradation of the SOI-LIGBT should be evaluated by the degradation of saturation current under the Vgmax stress condition. In addition, a novel SOI-LIGBT structure with an external p-type region was also proposed, which can alleviate the damage in the channel region by reducing the lateral electric field peak. Our experimental results demonstrate that the proposed structure could optimize the hot-carrier reliability effectively with the other characteristics maintained.

Second Harmonic Generation characterization of SOI wafers: Impact of layer thickness and interface electric field

In this work, we investigate Second Harmonic Generation (SHG) as a non-destructive characterization method for Silicon-On-Insulator (SOI) materials. For thick SOI stacks, the SHG signal is related to the thickness variations of the different layers. However, in thin SOI films, the comparison between measurements and optical modeling suggests a supplementary SHG contribution attributed to the electric fields at the SiO2/Si interfaces. The impact of the electric field at each interface of the SOI on the SHG is assessed. The SHG technique can be used to evaluate interfacial electric fields and consequently interface charge density in SOI materials.

SiGe-on-insulator fabricated via germanium condensation following high-fluence Ge+ ion implantation

Germanium condensation is demonstrated using a two-step wet oxidation of germanium implanted Silicon-On-Insulator (SOI). Samples of 220 nm thick SOI are implanted with a nominal fluence of 5 × 1016 cm−2 Ge+ at an energy of 33 keV. Primary post-implantation wet oxidation is performed initially at 870 °C for 70 min, with the aim of capping the sample without causing significant dose loss via Ge evaporation through the sample surface. This is followed by a secondary higher temperature wet oxidation at either 900 °C, 1000 °C, or 1080 °C. The germanium retained dose and concentration profile, and the oxide thickness is examined after primary oxidation, and various secondary oxidation times, using Rutherford backscattering analysis. A mixed SiGe oxide is observed to form during the primary oxidation followed by a pure silicon oxide after higher temperature secondary oxidation. The peak germanium concentration, which varies with secondary oxidation condition, is found to range from 43 at. % to 95 at. %, while the FWHM of the Ge profile varies from 13 to 5 nm, respectively. It is also observed that both the diffusion of germanium and the rate of oxidation are enhanced at 870 and 900 °C compared to equilibrium expectations. Transmission electron microscopy of a representative sample with secondary oxidation at 1080 °C for 20 min shows that the SiGe layer is crystalline in nature and seeded from the underlying silicon. Raman spectroscopy is used to determine residual strain in the SiGe region following secondary oxidation. The strain is compressive in nature and increases with Ge concentration to a maximum of approximately 1% in the samples probed. In order to elucidate the physical mechanisms, which govern the implantation-condensation process, we fit the experimental profiles of the samples with a model that uses a modified segregation boundary condition; a modified linear rate constant for the oxidation; and an enhanced diffusion coefficient of germanium where the enhancement is inversely proportional to the temperature and decays with increasing time. Comparison of the modeled and experimental results shows reasonable agreement and allows conclusions to be made regarding the dominant physical mechanisms, despite the semi-empirical nature of the model used.

Resonant pitch and roll silicon gyroscopes with sub-micron-gap slanted electrodes: Breaking the barrier toward high-performance monolithic inertial measurement units

This paper presents the design, fabrication, and characterization of a novel high quality factor (Q) resonant pitch/roll gyroscope implemented in a 40 μm (100) silicon-on-insulator (SOI) substrate without using the deep reactive-ion etching (DRIE) process. The featured silicon gyroscope has a mode-matched operating frequency of 200 kHz and is the first out-of-plane pitch/roll gyroscope with electrostatic quadrature tuning capability to fully compensate for fabrication non-idealities and variation in SOI thickness. The quadrature tuning is enabled by slanted electrodes with sub-micron capacitive gaps along the (111) plane created by an anisotropic wet etching. The quadrature cancellation enables a 20-fold improvement in the scale factor for a typical fabricated device. Noise measurement of quadrature-cancelled mode-matched devices shows an angle random walk (ARW) of 0.63° √h−1 and a bias instability of 37.7° h−1, partially limited by the noise of the interface electronics. The elimination of silicon DRIE in the anisotropically wet-etched gyroscope improves the gyroscope robustness against the process variation and reduces the fabrication costs. The use of a slanted electrode for quadrature tuning demonstrates an effective path to reach high-performance in future pitch and roll gyroscope designs for the implementation of single-chip high-precision inertial measurement units (IMUs).

Top-down technique for scaling to nano in silicon MEMS

Nanoscale building blocks impart added functionalities to microelectromechanical systems (MEMS). The integration of silicon nanowires with MEMS-based sensors leading to miniaturization with improved sensitivity and higher noise immunity is one example highlighting the advantages of this multiscale approach. The accelerated pace of research in this area gives rise to an urgent need for batch-compatible solutions for scaling to nano. To address this challenge, a monolithic fabrication approach of silicon nanowires with 10-μm-thick silicon-on-insulator (SOI) MEMS is developed in this work. A two-step Si etching approach is adopted, where the first step creates a shallow surface protrusion and the second step releases it in the form of a nanowire. It is during this second deep etching step that MEMS—with at least a 2-order-of-magnitude scale difference—is formed as well. The technique provides a pathway for preserving the lithographic resolution and transforming it into a very high mechanical precision in the assembly of micro- and nanoscales with an extreme topography. Validation of the success of integration is carried out via in situ actuation of MEMS inside an electron microscope loading the nanowire up to its fracture. The technique yields nanowires on the top surface of MEMS, thereby providing ease of access for the purposes of carrying out surface processes such as doping and contact formation as well as in situ observation. As the first study demonstrating such monolithic integration in thick SOI, the work presents a pathway for scaling down to nano for future MEMS combining multiple scales.

High-Voltage Integrated Circuits: History, State of the Art, and Future Prospects

High-voltage ICs (HVICs) are used in many applications, including ac/dc conversion, off-line LED lighting, and gate drivers for power modules. This paper describes the technologies most commonly used in commercial HVICs, including junction-isolation, thin silicon-on-insulator (SOI), and thick SOI approaches. Emerging technologies such as thin silicon membrane are also discussed.

Composition and stress of SiGe nanostructures on curved substrates

Recent experimental studies of Ge nanoislands on silicon-on-insulator (SOI) substrates have provided a defect-free strain relaxation mechanism through the bending of the substrate. Here, using atomistic Monte Carlo simulations and analytical modeling, we couple this relaxation mechanism with interdiffusion and alloying and observe composition profiles that are completely different from those observed in flat nanoislands. Moreover, for comparable SOI and island thicknesses, intermixing can be greatly reduced and Ge content in the islands is highly preserved.

250 V Thin-Layer SOI Technology With Field pLDMOS for High-Voltage Switching IC

A 250 V thin-layer SOI technology based on a 1.5- $\mu \text{m}$ -thick SOI layer is developed for high-voltage (HV) switching IC. HV thin-layer silicon on insulator (SOI) field p-channel LDMOS (pLDMOS) with thick gate oxide layer, SOI RESURF n-channel LDMOS (nLDMOS) with thin gate oxide layer, and low-voltage CMOS are monolithically integrated. Compared with the conventional SOI technology integrating field pLDMOS, the thickness of SOI layer is reduced from above 5 $\mu \text{m}$ to only 1.5 $\mu \text{m}$ . The field implant (FI) technology is adopted to eliminate channel discontinuity underneath the bird’s beak and achieve shallow junction depth to avoid back gate (BG) punchthrough breakdown for the field pLDMOS. A BG punchthrough model is presented with simulation results. The field pLDMOS with breakdown voltage (BV) of −329 V and RESURF nLDMOS with BV of 338 V are experimentally realized. A 250 V switching IC using the field pLDMOS and RESURF nLDMOS as the level-shift and the output stage is also presented based on the developed thin-layer SOI technology.

Modeling of Drain Electric Flux Passing Through the BOX Layer in SoI MOSFETs—Part II: Model Derivation and Validity Confirmation

Increased drain-induced barrier lowering caused by drain electric flux (or field) passing through the buried-oxide (BOX) layer in silicon-on-insulator (SoI) MOSFETs has been reported as an inherent disadvantage of SoI technology. Part I of this paper discussed derivation of the relationships between coordinates in MOSFETs and potential/stream function in preparation for the modeling of electric flux using conformal mapping in subthreshold regions of ground plane SoI MOSFETs and the validity of the approach was checked via device simulation. Here, in Part II of this paper, we discussed the model's derivation based on these relationships. The dependences of the flux amount on BOX thickness, BOX permittivity, SoI thickness, and gate length estimated using the model were also discussed in comparison with those estimated via device simulation.