A Novel DRAM Cell Structure with Parasitic Storage Capacitance for SoCs on SoI Wafer in 65nm Planar MOS Technology

Abstract

A novel 65nm Dynamic Random access memory (DRAM) cell, namely capacitor less RectFET based DRAM cell (CLRDC) is explored in silicon-on-insulator (SoI) wafer for embedded-DRAM (eDRAM) for system-on-chip (SoC), applications with Rectangular FET (RectFET) as its pass-transistor (PT). This CLRDC exploits its parasitic surround buried oxide capacitance (SBC) of SoI-wafer around RectFET (source) for realizing its ‘charge storage capacitance (Cs). For Cs=30fF (femtoFarad) target, it’s found to need an area factor of 4.3µm2 with 5nm thick SoI buried-oxide. This SoI wafer is explored to yield a capacitance density Cbuox=6.91 fF/µm2. The DC parameters of the PT are found to be very sensitive to process anneal temperature (Ta) and so are its DC characteristics too. A 2% increase in the Ta from a nominal 1000oC has resulted in an increase of 30% and 1.1% in the RectFET’s leakage (Idsat-off=I-off) and on-state (Idsat-on=I-on) currents respectively. The CLRDC cell transfer ratio T is also found to be a function of small signal frequency (f), Ta, and source/drain bias voltages Vs/Vd, respectively. And finally the retention characteristics of this CLRDC is again found to be a function of I-off and I-on currents of RectFET, when studied at RectFET’s (drain) supply voltage VDD=1.2V.