Abstract
Increased drain-induced barrier lowering caused by drain electric flux (or field) passing through the buried-oxide (BOX) layer in silicon-on-insulator (SoI) MOSFETs has been reported as an inherent disadvantage of SoI technology. Part I of this paper discussed derivation of the relationships between coordinates in MOSFETs and potential/stream function in preparation for the modeling of electric flux using conformal mapping in subthreshold regions of ground plane SoI MOSFETs and the validity of the approach was checked via device simulation. Here, in Part II of this paper, we discussed the model's derivation based on these relationships. The dependences of the flux amount on BOX thickness, BOX permittivity, SoI thickness, and gate length estimated using the model were also discussed in comparison with those estimated via device simulation.
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