Ge Layer Thickness Research Articles

High efficiency thin-film crystalline Si/Ge tandem solar cell

We propose and simulate a photovoltaic solar cell comprised of Si and Ge pn junctions in tandem. With an anti-reflection film at the front surface, we have shown that optimal solar cells favor a thin Si layer and a thick Ge layer with a thin tunnel hetero-diode placed in between. We predict efficiency ranging from 19% to 28% for AM1.5G solar irradiance concentrated from 1 approximately 1000 Suns for a cell with a total thickness approximately 100 microm.

Selective epitaxial growth of Ge(1 1 0) in trenches using the aspect ratio trapping technique

The aim of this study was to assess the efficiency of aspect ratio trapping in improving the crystalline quality of relaxed Ge(1 1 0) layers selectively grown in trenches surrounded by SiO 2. The 400 °C growth of a few hundreds of nanometers thick Ge layers has first been studied on blanket Si(1 1 0) surfaces then in recessed areas of Si(1 1 0) patterned wafers. The influence of 1 min H 2 anneals (in-between 600 and 850 °C) on the surface morphology, crystalline quality and strain state of blanket Ge(1 1 0) layers has notably been quantified. Intermediate annealing temperatures (750 °C) have improved the crystalline quality and increased the macroscopic strain relaxation of those layers, without too high a surface roughening. (1 1 0) Si windows (surrounded by shallow trench isolation) of patterned wafers have then been recessed by ≈300 nm using gaseous HCl, with a definite faceting and a slight roughening of the resulting cavities. Epitaxial lateral overgrowth of Ge has then been implemented in those trenches, followed by 1' H 2 bakes at 750 °C. Chemical mechanical polishing has been used afterwards to get rid of the several hundreds of nm thick Ge layer overflowing on the SiO 2 areas (very reduced dishing and flat Ge(1 1 0) surfaces obtained in the end). The efficiency of aspect ratio trapping in reducing the defect density in those Ge(1 1 0) layers is not obvious. Indeed, some trapping of inclined defects in the SiO 2 sidewalls of narrow Ge(1 1 0) patterns (∼80 nm long) has been evidenced. However, the theoretically unexpected appearance of defects at 90° to the surface (i.e. normal to (1 1 0)) that were consequently not trapped was detrimental to defect density reduction. Those 90° defects may have arisen from interactions of inclined defects with one another. The reduction of the high defect density in relaxed (1 1 0) layers is thus still challenging and requires further investigations.

High Quality Strained Ge Epilayers on a Si[sub 0.2]Ge[sub 0.8]/Ge/Si(100) Global Strain-Tuning Platform

High structural quality, compressively strained Ge surface epilayers have been grown on Si(100) substrates of up to 200 mm diameter. The epitaxial growth by industrially compatible reduced pressure chemical vapor deposition proceeded uninterruptedly via an intermediate relaxed Si0.2Ge0.8/Ge buffer. In-depth characterization of the epilayers revealed a relatively smooth surface and a low threading dislocation density. The Ge layers were demonstrated to remain fully strained for thicknesses of more than 100 nm. The high quality of the material and flexibility to choose the Ge layer thickness over a wide range make these heterostructures very attractive for fabricating various electronic and photonic devices. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3482159] All rights reserved.

Impact of the H 2 anneal on the structural and optical properties of thin and thick Ge layers on Si; Low temperature surface passivation of Ge by Si

Using a low temperature/high temperature strategy, we have grown thin (0.27 μm) and thick (2.45 μm) Ge layers on Si(0 0 1) substrates that we have submitted to various constant temperature (750 °C) or cyclic (750 °C/890 °C) H 2 anneals, the objective being to identify those yielding the smoothest surfaces, the lowest threading dislocations densities (TDDs) and the highest near infra-red optical absorptions. The best trade-off for thin layers was 750 °C, 60 min H 2 anneals. Using longer duration 750 °C anneals and especially 750 °C/890 °C cyclic anneals indeed yielded rougher surfaces and vastly degraded optical absorption (deleterious formation of GeSi alloys). By contrast, short 750 °C/890 °C thermal cyclings yielded the best metrics in thick Ge layers (while being at the same time the best in terms of throughput): root mean square surface roughness around 0.8 nm, TDD around 10 7 cm −2, slightly tensily-strained layers (which a plus for optical absorption as the absorption edge is shifted to higher wavelengths), a limited penetration of Si into Ge (and thus absorption coefficients at 1.3 and 1.55 μm almost equal to those of as-grown layers), etc. We have also described the low temperature (450 °C/525 °C) process that we have developed to passivate Ge surfaces thanks to SiH 4 prior to gate stack deposition. Si layer thickness should be below 20 Å in order to have conformal deposition. A transition of the growth front to 3 dimensions has indeed been evidenced for 20 Å and higher.

Fabrication of high quality Ge virtual substrates by selective epitaxial growth in shallow trench isolated Si (001) trenches

To further boost the CMOS device performance, Ge has been successfully integrated on shallow trench isolated Si substrates for pMOSFET fabrication. However, the high threading dislocation densities (TDDs) in epitaxial Ge layers on Si cause mobility degradation and increase in junction leakage. In this work, we studied the fabrication of Ge virtual substrates with low TDDs by Ge selective growth and high temperature anneal followed by chemical mechanical polishing (CMP). With this approach, the TDDs in both submicron and wider trenches were simultaneously reduced below 1 × 10 7 cm − 2 for 300 nm thick Ge layers. The resulting surface root-mean-square (RMS) roughness is about 0.15 nm. This fabrication scheme provides high quality Ge virtual substrates for pMOSFET devices as well as for III–V selective epitaxial growth in nMOSFET areas. A confined dislocation network was observed at about 50 nm above the Ge/Si interface. This dislocation network was generated as a result of effective threading dislocation glide and annihilation. The separation between the confined threading dislocations was found in the order of 100 nm.

Synthesis of strained SiGe on Si(100) by pulsed laser induced epitaxy

Pulsed laser induced epitaxy (PLIE), based on melting/solidification processes induced by nanosecond laser pulses, is used to synthesize pseudomorphic Si 1 − x Ge x epilayers from 20 to 80 nm thick Ge layers evaporated on a Si(100) wafer. Ge concentration and strain are characterized by transient reflectivity, energy dispersive X-ray analysis and X-ray diffraction from symmetric (004) and asymmetric (224) reflections. For a low Ge thickness or a high laser fluence, PLIE builds up only a pseudomorphic strained Si 1 − x Ge x layer with a graded Ge composition reaching x ≈ 19% near the surface. When the Ge amount is in excess to achieve this situation, PLIE forms additionally a relaxed Si 1 − x Ge x layer with x values up to ≈40% over the previous pseudomorphic layer.

Epitaxial growth of Ge thick layers on nominal and 6° off Si(0 0 1); Ge surface passivation by Si

We have grown various thickness Ge layers on nominal and 6° off Si(0 0 1) substrates using a low-temperature/high-temperature strategy followed by thermal cycling. A combination of ‘mounds’ and a perpendicular cross-hatch were obtained on nominal surfaces. On 6° off surfaces, three sets of lines were obtained on top of the ‘mounds’: one along the ⟨1 1 0⟩ direction perpendicular to the misorientation direction and the other two at ∼4.5° on each side of the ⟨1 1 0⟩ direction parallel to the misorientation direction. The surface root mean square roughness was less than 1 nm for 2.5 µm thick nominal and 6° off Ge layers. Those slightly tensily strained Ge layers (R ∼ 104%) were characterized by 5 × 107 cm−2 (as-grown layers) −107 cm−2 (annealed layers) threading dislocation densities, independently of the substrate orientation. We have then described the 550 °C/650 °C process used to passivate nominal Ge(0 0 1) surfaces with Si prior to gate stack deposition. An ∼5 Å thick SiGe interfacial layer is self-limitedly grown at 550 °C and then thickened at 650 °C (5 Å min−1) thanks to SiH2Cl2 at 20 Torr. Such a Ge surface passivation yields state-of-the-art p-type metal oxide semiconductor field effect transistors provided that 15 Å Si layer thickness is not exceeded. For higher thickness, elastic strain relaxation (through the formation of numerous 2D islands) occurs, followed by plastic relaxation (for a 35 Å thick Si layer).

Swift-heavy-ion-induced shaping of spherical Ge nanoparticles into disks and rods

The work reports on experimental features and theoretical studies of swift-heavy-ion-induced shaping of Ge nanospheres into disks. A stack of alternating Ge and SiO2 layers was sputtered on an oxidized Si wafer. The Ge layer thicknesses varied from 2.5 to 7.5nm. Thermal treatment above the melting temperature of Ge transformed each Ge layer into a layer of Ge nanospheres. With growing Ge layer thickness the mean diameter increases from 8 to 37nm. Irradiation with low fluences (∼1014cm−2) of 38MeV I7+ shaped medium-sized Ge nanospheres into disks, whereas smaller ones became rod-like and larger ones remained unchanged. At higher fluences, the larger Ge nanospheres shrink due to Ge loss and shape into disks too. A new model is presented and atomistic Monte-Carlo simulations are shown which describe the shaping evolution and the size thresholds for shaping quantitatively. The volume change of Ge upon melting has been identified as driving force.

Epitaxial Growth of Ge Thick Layers on Nominal and 6oC off Si(001); Ge Surface Passivation by Si

In the first part of this paper, we have quantified the surface roughness, the degree of strain relaxation and the defect density in thick Ge layers grown using a low temperature / high temperature approach on nominal and 6oC off (towards one of the <110> directions) Si(001) substrates. In the second part, we have succinctly described the Si passivation process we use on Ge prior to gate stack formation in order to obtain high performance p-type metal oxide semiconductor field effect transistors.

Activation level in boron-doped thin germanium-on-insulator (GeOI): Extraction method and impact of mobility

We hereby present a non-destructive method for extracting the activation level on boron-doped germanium-on-insulator (GeOI) wafers, with a discussion on the impact of the hole mobility model. This method combines Monte Carlo boron profile simulations with optical Ge layer thickness T Ge and electrical sheet resistance R sh measurements. As B atoms are known not to diffuse in Ge for the usual activation temperatures (<800 °C), we can assume that the as-implanted dopant profile remains unchanged after annealing (no modelling of boron diffusion required). We highlight that the knowledge of the hole mobility dependence on activated impurities concentration in Ge is of paramount importance. Several experimental and theoretical models are available in the literature. After relative validity assessments, all of them have been implemented for extraction and unfortunately yield different values scattered over nearly one decade. Still, the lower-bound concentration 2.7×10 19 cm −3 is in the range of the state-of-the-art values for B-implanted crystalline Ge and has proven suitable for functional GeOI pMOSFET demonstration.

Reduced pressure chemical vapor deposition of Ge thick layers on Si(0 0 1), Si(0 1 1) and Si(1 1 1)

We have carried out an in-depth structural study of Ge thick layers grown using the so-called “LT/HT” approach on Si(0 0 1), Si(0 1 1) and Si(1 1 1) wafers. The low temperature (400 °C) adopted for the first Ge layer plastically relaxes the strain in the Ge film without 3D islanding. The high temperature (750 °C) used for the growth of the second, topmost, Ge layer lowers the dislocation density and reduces the overall deposition time. High temperature thermal cycling (in-between 750 and 890 °C) was called upon to further reduce the amount of defects in the layers. Ge growth rates on (0 0 1) were consistently higher than the ones on (1 1 1), which were themselves higher than on (0 1 1) (be it at 400 °C, 100 Torr or at 750 °C, 20 Torr). The surfaces of Ge (0 0 1) layers were rather flat, as attested by their small root mean square (rms) roughness and Z ranges (<1 and 10 nm, respectively). By contrast, Ge (0 1 1) (Ge (1 1 1)) thick layers were really rough, with rms roughness and Z ranges typically 30 (60) times higher than on (0 0 1). Almost all Ge layers were in a tensile-strain configuration, with macroscopic degrees of strain relaxation in-between 101% and 106% (slightly higher on (1 1 1) than on (0 0 1) and on (0 1 1), however). Misfit dislocations were found (by cross-sectional transmission electron microscopy) to be confined in the first few hundreds of nanometres of 2.5 μm thick Ge layers on Si(0 0 1). As far as 2.5 μm thick Ge layers on (0 1 1) and (1 1 1) are concerned, numerous {1 1 1} stacking faults were present at the Ge/Si interface and also threading all the way to the surface. The threading “defect” density, which is close to 10 7 cm −2 on (0 0 1), is around 8×10 8 cm −2 on (0 1 1) and roughly 2×10 9 cm −2 on (1 1 1). The higher defect density on (0 1 1) and (1 1 1) is likely due to 60° misfit dislocations dissociation (into 30° and 90° partial dislocations). For such surface orientations, the 90° partial dislocation is expected to lead with in its trail the 30° partial dislocation (hence the stacking faults multiplication).

Reduced Pressure–Chemical Vapour Deposition of Si/SiGe heterostructures for nanoelectronics

We have first of all quantified the impact of pressure on Si and SiGe growth kinetics. Definite growth rate and Ge concentration increases with the pressure have been evidenced at low temperatures (650–750 °C). By contrast, the high temperature (950–1050 °C) Si growth rate either increases or decreases with pressure (gaseous precursor depending). We have then described the selective epitaxial growth process we use to form Si or Si 0.7Ge 0.3:B raised sources and drains on ultra-thin patterned Silicon-On-Insulator (SOI) substrates. We have afterwards presented the specifics of SiGe virtual substrates and of the tensile-strained Si layers grown on top (used as templates for the elaboration of tensily strained-SOI wafers). The tensile strain, which can be tailored from 1.3 up to 3 GPa, leads to an electron mobility gain by a factor of 2 in n-Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) built on top. High Ge content SiGe virtual substrates can also be used for the elaboration of compressively strained Ge channels, with impressive hole mobility gains (×9) compared to bulk Si. After that, we have described the main structural features of thick Ge layers grown directly on Si (that can be used as donor wafers for the elaboration of GeOI wafers or as the active medium of near infrared photo-detectors). Finally, we have shown how Si/SiGe multilayers can be used for the formation of high performance 3D devices such as multi-bridge channel or nano-beam gate-all-around FETs, the SiGe sacrificial layers being removed thanks to plasma dry etching, wet etching or in situ gaseous HCl etching.

Epitaxial Growth of Ge Thick Layers on Nominal and 6{degree sign}C off Si(001); Ge Surface Passivation by Si

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Benefits and side effects of high temperature anneal used to reduce threading dislocation defects in epitaxial Ge layers on Si substrates

In the first part of this work we studied the effect of annealing time and temperature on the degree of threading dislocations density (TDD) reduction in epitaxial Ge films grown by CVD on Si. We show, that one-step controlled nitrogen annealing at temperatures above 800 °C can decrease TDD of thick (1.6 µm) Ge layers with 1 order of magnitude from 1E+ 08/cm 2 down to 1E+ 07/cm 2. Our results indicate that when temperature is high enough (> 800 °C) time does not play a role anymore. Thus for a temperature of 850 °C the same degree of TDD reduction can be achieved for 3 as well for 30 min. In the second part of the work we demonstrate that the combination of cycled epi growth and high temperature annealing although beneficial for TDD reduction deteriorates the crystalline quality of the layers due to significant Si out-diffusion and SiGe formation. Ge on Si substrates with lower defect densities have been further characterized by leakage current measurements on diode structures. Our results indicate that the reduction of drain to bulk leakage is insignificant and does not correspond to 1 order of magnitude reduction in TDD. We therefore conclude that threading dislocations are not the dominant factor for reduced device performance.

Wet cleaning and surface characterization of Si 1− xGe x virtual substrates after a CMP step

New reactants such as ozone dissolved in ultra-pure water have been widely used the last few years instead of the original Radio Corporation of America (RCA) cleaning (which is a combination of the Standard Cleaning 1 (SC1) and the Standard Cleaning 2 (SC2)). In a first part of the study (Microelectron. Eng. 83 (2006) 1986), we had quantified the efficiency of a new cleaning sequence (that calls upon HF and H 2O/O 3 solutions) on polished Si 1− x Ge x virtual substrates ( x = 0.2–0.5). We are discussing here the surface morphology and wetability together with the oxide thickness and structure typically obtained after this so-called “DDC-SiGe” wet cleaning. Flat surface morphologies are found after cleaning whatever the Ge content (from 20 to 50%). Typical root mean square roughness is around 0.4 nm. We have used X-ray Photoelectron Spectroscopy to determine the characteristics of the surface termination after this “DDC-SiGe” cleaning. An oxide mainly composed of SiO 2 is formed, with a low fraction of Ge sub-oxide and GeO 2. The distribution of chemical species is not that different from the one obtained after the use of a SC1 cleaning. However, the chemical oxide formed is slightly thicker. Such a HF/O 3 cleaning leads, when used on thick Ge layers grown on Si, to the formation of a really thin Ge sub-oxide. Our oxidation model assumes a competition in O 3 solutions between the oxidation rates of Si and Ge atoms (faster for Si) and the dissolution of the Ge oxide formed in solution. This mechanism, which implies the formation of a slightly porous oxide, is different from the one seeming to occur in SC1-based solutions. Indeed, the addition of surfactant in a SC1 solution modifies the oxidation rate compared to standard SC1 or O 3-based solutions, suggesting a diffusion of reactants towards the interface between the SiGe and the oxide in formation, assisted by the reactions of species within the cleaning solutions.

Laser-induced self-organization in silicon-germanium thin films

We report on the formation of self-organized structures in thin films of silicon-germanium (Si1−xGex) with 0.3&amp;lt;x&amp;lt;0.7 after exposing the films to laser irradiation. Amorphous SiGe samples that are exposed to a single laser pulse exhibit a ripple structure that changes to a hillock structure when the samples are irradiated with additional laser pulses. The topographic structure is coupled to a periodic compositional variation of the SiGe alloy. The periodicity length of the structure after a single laser pulse is in the range of 0.3–1.1 μm, depending on Ge content, layer thickness, and laser fluence, and rapidly grows with increasing number of laser pulses. In situ conductivity measurements during solidification support the theoretical instability analysis that we have done, based on the Mullins–Sekerka theory, to elucidate the nature of this phenomenon. Moreover, as theoretically predicted, the self-organization phenomenon can be turned off by increasing the solidification velocity.

Photoluminescence of Ge nanocrystals self-assembled on SiO 2

Ge nanocrystals have been obtained from the dewetting process during thermal annealing of an amorphous Ge layer deposited by molecular beam epitaxy on a thin SiO 2 layer on Si(001). The Ge nanocrystals were then capped with a thin layer of amorphous Si. The mean nanocrystal size–2.5–60 nm–depends on the initial Ge layer thickness. Low-temperature photoluminescence (PL) measurements were performed to investigate quantum confinement effects on the Ge nanocrystal energy gap and defect states. For the present range of particle sizes, the nanoparticle PL emission appeared as a wide near-infrared band near 900 meV although a weak confined band was also observed for the smallest nanoparticles. Further thermal annealing of the samples increased the interband recombination by nearly two orders of magnitude.

Ge nanocrystals formation on SiO2by dewetting: application to memory

Ge nanocrystals (NCs) are produced by a dewetting process during annealing of an amorphous Ge layer deposited on an ultra thin SiO2 layer. We have investigated the characteristics of the resulting NCs as a function of the nominal Ge layer thickness. Thanks to transmission electron microscopy images, we have extracted both the wetting angle and the NCs aspect ratio. We found that these characteristics remain constant whatever is the nominal thickness in the range of 1.5 to 10 nm. These results suggest that NCs have reached their equilibrium shape. We also experimentally determined the evolution of the NCs with the nominal thickness of the amorphous layer and found a linear relation. These results are in agreement with mass conservation and energetical considerations. Moreover a memory effect was evidenced in all the samples by C − V measurements. At last, we demonstrate that the use of a patterned SiO2 surface improves considerably the ordering of NCs and reduces their size distribution. Such a process is promising for future integration of NCs in memory devices.

Facet formation and lateral overgrowth of selective Ge epitaxy on SiO2-patterned Si(001) substrates

Faceting and lateral overgrowth have been investigated for Ge selectively grown on Si(001) substrates in trench regions bound by SiO2 sidewalls. In wet-etched large trenches with sloped sidewalls, Ge faceting behavior was similar to Si and SixGe1−x faceting: slow-growing {113} facets dominate, with {111} facets expanding as the layer became thicker. However, the {111} facet length for Ge was much smaller than that of Si; this can be explained in terms of mass transport and accumulation, as well as energy minimization and the higher surface diffusivity of Ge. In dry-etched small trenches with vertical sidewalls, minimization of the high-energy interface area between Ge and SiO2 appears to be most critical in determining faceting morphology. Overgrowth of Ge led to void formation at the oxide interface, presumably to avoid the high-energy Ge/SiO2 interface. Upon coalescence of lateral-growth regions, fast-growing (001) forms and dominates subsequent growth. Thus, the total thickness of the overgrown Ge layer was closely related to the width of the SiO2 region between trenches.

PE-CVD fabrication of germanium nanoclusters for memory applications

We have investigated Ge nanoclusters (Ge-NC) embedded in silicon dioxide, whose fundamental properties promise improved characteristics in NC flash memory devices as compared to Si nanoclusters. We present a simple new method, based on plasma-enhanced CVD (PE-CVD) deposition of amorphous Ge (a-Ge) onto SiO 2, to create gate stacks with embedded Ge-NC at vertically well-controlled positions suitable for use in flash memory devices. This process minimizes the exposure of Ge to environmental influences by depositing a-Ge as well as a SiO 2 cap layer in situ within the same deposition chamber. Subsequent high-temperature anneals compatible with the temperature budget of CMOS processing are used for the actual cluster formation. Variation of annealing temperature and duration of this step as well as the thickness of the initial Ge layer controls the average cluster radius and density, as determined by transmission electron microscopy (TEM). Measurements of electrical properties show the capability of samples with NC to store charge.