Thermal Vias Research Articles

Assembly of Large Flip Chip Die in Ceramic Packages

Hermetic packaging is required to ensure the reliability of processors and application specific integrated circuit (ASIC) chips that are used in strategic systems, whose operating lifetimes typically exceed thirty years. Performance requirements for emerging system applications are dictating the need for one thousand or more I/O, which precludes the use of wire bonded devices. These packaging requirements can be met by flip chip bonding die onto multilayer, high temperature cofired ceramic substrates. The hermetic environment is provided by a Kovar metal ring that is brazed onto the ceramic and sealed in the final assembly step, by welding on a metal cover. Several process and design requirements must be met to achieve high reliability flip chip assemblies. Reflowed devices must be free of flux residues because they are corrosive, provide a path for ion diffusion, are a source of moisture and degrade the adhesion of underfill to chip and substrate. Removal of flux residues by cleaning is problematic because the gap between chip and substrate is very small relative to chip area. A better approach is to bond chips without flux, as we do, by reflowing them in a formic acid environment. An important reliability requirement for strategic hardware is the ability to sustain many cycles over extended temperature ranges. Temperature cycles induce plastic deformation in the solder connections as a result of stresses generated by the mismatch in thermal expansion coefficients of the chip and package. These stresses can be reduced significantly by underfilling the bonded chip with a filled adhesive. Choice of material as well as process execution impact the effectiveness of underfill enhancement of reliability. Optimization of both the physical design and composition of the solder connections is essential to producing reliable flip chip assemblies. We make extensive use of finite element analyses (FEA) in which we track the accumulation of plastic strain energy in the solder connections as they are subjected to temperature cycle induced stresses. Good correlations between the energy accumulated per cycle and the number of cycles to failure can be achieved if accurate state models of the solder are used. We have a catalog of Anand models for the solder compositions that we use in our FEA simulations. One of the more challenging aspects of designing high performance flip chip packages is matching the size and pitch of the bond pads on the ceramic with those on the chip. Current devices use 90 micron diameter pads on 200 micron pitch, but newer designs are migrating towards 80 micron diameter pads on 180 micron pitch. It challenging to maintain tight tolerances on pad geometries in these higher density packages and to route all the additional signals. Thermal management is also an important component of the package design. Thermal vias and thermally conductive underfills are used to remove heat from the front side of the chip. On the backside of the chip, the gap between chip and cover is minimized and filled with a high thermal conductivity interface material. High fidelity FEA modeling is necessary to ensure that the chip can be adequately cooled in its hermetic environment. This paper discusses the impact of these design and assembly factors on the reliability of high performance, hermetically packaged flip chip assemblies.

Investigations of Li-Ion Battery Thermal Management Systems Based on Heat Pipes: A Review

Investigations of Li-Ion Battery Thermal Management Systems Based on Heat Pipes: A Review

(Invited) Modified SAB Methods for Hybrid and All-Cu Bonding for 3D Integration below 200ºC

Two methods of Surface Activated Bonding (SAB) will be proposed to enable low-temperature hybrid bonding for 3D integration.A modified one involves surface activation processes using Ar fast-atom-beam bombardment with simultaneous co-sputtering of Si nano-adhesion layer, followed by sequential plasma irradiation with N2 radicals. These processes combine hydrophilic treatment and bonding in a low-vacuum chamber. The Si nano-adhesion layer and the sequential plasma treatment appear to enhance hydrophilicity, which enables low-temperature bonding of both Si oxides and Cu pads as hybrid bonding. Bonding in a low-vacuum environment helps to avoid void generation caused by air entrainment.The other one is the standard SAB. But we will connect two device wafers not in a hybrid bonding but in all-Cu bonding. A small insulation layer surrounds the area around the Cu electrode on the wafers, while the rest is covered with Cu solid layers. These solid layers constitute the ground layer, power layer, or their paired layers and may contribute to heat dissipation when connected to thermal vias. The two wafers are connected only by bonding on the Cu electrodes and solid layers. The insulating parts around the Cu electrodes do not necessarily have to be bonded, and the gaps may be kept in a vacuum. Of course, the bonded surfaces need to be flattened, and a new division and layout design of the solid electrode will be required.Cu-Cu direct bonding is possible at room temperature by applying the standard SAB directly. Of course, this requires bonding in an ultra-high vacuum condition, which inevitably reduces the throughput. However, room temperature bonding is overwhelmingly advantageous for bonding different types of devices and wafers. It is expected to become a powerful tool for 3D heterogeneous integration of devices in the future. Figure 1

Toward Thinner and Higher Heat Dissipation Advanced Chip Embedded Power Supply Module Packaging

Along with power management complexity, small/thin and high efficiency power supply devices such as DCDC converters and Inverters needs are increasing. In response, several chip-embedded packages have been proposed, but their size/thickness, heat dissipation properties, and cost necessitate the development of further concepts. In this report, we propose novel chip-embedded package that uses Semi-additive metallization with non-prepreg coreless substrate and 300 mm square Panel-level manufacturing for cost competitiveness. In the case of a prepreg substrate, it is difficult to make large thermal vias due to presence of glass cloth and the presence of the substrate core makes thickness reduction difficult. Because of such difficulties, prepreg substrate packages have limited characteristics around thermal performance and thickness. Our proposed structure has excellent heat dissipation and minimized thickness due to using thin non-prepreg coreless substrates that allows for large thermal vias by a laser drill and the thin package. We performed thermal resistance simulations and found that our package improved up to 43% as compared to the prepreg package. And also, our build-up interlayer material has close CTE to Cu-RDL and a low Young’s modulus that is effective in reducing package warpage. As a result of simulation, package warpage after post-curing is just 1/10th of that of the prepreg package, this means highly reliable on board. Developments using Si power die will be reviewed. We believe our proposed new package is also suitable for high performance package utilizing GaN and SiC.

(Invited) Modified SAB Methods for Hybrid and All-Cu Bonding for 3D Integration below 200ºC

Two Surface Activated Bonding (SAB) methods will be proposed to enable low-temperature hybrid bonding for 3D integration. A modified one involves surface activation processes using Ar fast-atom-beam bombardment with simultaneous co-sputtering of Si nano-adhesion layer, followed by sequential plasma irradiation with N2 radicals. In the other one, we will connect two device wafers not in a hybrid but all-Cu bonding. A small insulation area surrounds the Cu pads on the wafer, while the rest is covered with Cu solid layers. These solid layers constitute the ground plane, power plane, or their paired layers and may contribute to heat dissipation when connected to thermal vias. The two wafers are connected only by bonding on the Cu electrodes and solid layers. Cu-Cu direct bonding is possible at room temperature by applying the standard SAB directly. Room-temperature bonding is overwhelmingly advantageous for bonding heterogeneous devices and wafers.

Modeling the Effects of Thermal Pad Voiding on Quad Flatpack No-lead (QFN) Components

Finite element modeling was used to evaluate the effects of thermal pad solder voiding on the thermal resistance of Quad Flatpack No Lead components. This included two different approaches for modeling solder voids: many small, distributed voids, the effects of which were averaged across the entire solder contact area or a single discrete void. Two approaches were used for defining the thermal path established in the solder. The effects of other design parameters - thermal boundary conditions, the presence of thermal vias under the package, and the size of the die power dissipation area – were also addressed. Modeling showed that thermal vias and external boundary conditions had the most significant impact on the package thermal resistance. Solder pad voids and concentrated die-level heat dissipation, for the range used in this study, had noticeable but less significant impacts on thermal resistance. The study also compared different approaches for simulating solder voiding and identified ranges in which modeling simulations are most appropriate.

Thermal and mechanical reliability of thermal through-silicon vias in three-dimensional integrated circuits

This research aims to explore the influences of shapes, structures, and arrangements of thermal through-silicon vias (TTSVs) on the thermal and mechanical reliability of a three-dimensional integrated circuit (3D IC). For this purpose, a finite element model coupling the temperature and stress fields in a representative 3D IC with three layers of dies was established to allow numerical simulation of thermal and mechanical reliability caused by the above three factors. The research results show that firstly, rectangular TTSVs have better heat transfer performance than commonly used circular TTSVs of the same area. However, the former is more likely to cause problems pertaining to mechanical reliability in dies. Secondly, compared with the in-line mode of arrangement, the staggered arrangement mode can enable the more compact and uniform arrangement of TTSVs and improve the capacity for heat conduction between adjacent TTSVs, thus reducing the hotspot temperature: meanwhile, the thermal stress rises giving rise to a contradiction between the conventional means of enhancing the heat transfer performance of TTSVs and the resulting increase of thermal stress. Finally, by adding air gaps to TTSVs, the thermal stress around TTSVs can be reduced, while the heat transfer performance also decreases. If air gaps are replaced with carbon nanotubes (CNTs), such a problem can be alleviated. The analysis methods and research results can provide an important reference for the trade-off between thermal reliability and mechanical reliability in 3D ICs in engineering practice.

Integrating Diamond for Cooling Electronics

III-Nitrides promise to offer high-frequency power amplifiers at higher power densities. This is attractive for realizing device platforms for 5G and beyond. It also enables integrating Si-based electronics to complement functionalities. However, to obtain the full potential of III-Nitrides one must operate these transistors at higher power densities, for which thermal management is crucial.Due to the continuous need for higher performance in various applications ranging from DC to W-band frequencies, semiconductor devices are pushed to higher power densities. This results in a higher junction temperature owing to the Joule heating in the channel resulting in device performance degradation and premature failure. Using devices based on wide-bandgap (WBG) semiconductors such as Gallium Nitride (GaN) and Gallium Oxide (GaOx) with a larger critical electric field and high-temperature tolerance, one could increase the power density. However, in order to increase the output power to the levels that is promised by these wide bandgap materials, junction temperature reduction through device-level cooling is critical. We are actively researching thermal management at device, circuit and packaging level using synthetic polycrystalline (PC) diamond. PC-diamond, at an appropriate grain size offers a TC is higher than any competing thermal vias with metals without interfering the electrical performance. Over the past 5 years we have demonstrated the potential of integrating diamond with GaN and recently achieving a record low diamond/GaN thermal boundary resistance (TBR) along with a relatively high diamond thermal conductivity (TC). This remarkable thermal performance was be achieved by maintaining the electrical performance, as demonstrated by the unharmed channel charge and mobility results.There are two key requirements for thermal management using heat spreading from the channel: first, a low thermal boundary resistance (TBR) between the hot spot in the channel and the heat spreader is required (in this study between GaN channel and diamond). Second, a low thermal resistance path to the heat-sink is crucial from the diamond layer which is directly proportional to diamond’s thermal conductivity (TC). In collaboration with Univ of Bristol, we have reported a TBR of ~3 m2K/GW, to date, known to be the lowest reported TBR for GaN HEMT technology. Diamond-GaN TBR depends strongly on the interface smoothness and the thickness of interfacial Si3N4 layer. A thinner Si3N4 resulted in lower TBR and allowed superior phonon coupling from the channel to the spreader. We have also measured a remarkably high TC for a 2 μm-thick diamond layer yielding over 650 W/m.K. The diamond grains are near isotropic in shape that allows excellent in-plane and cross-plane thermal conductivity. Achieving high TC within a thin film of diamond, grown heterogeneously, underscores the importance of our technique, since it reduces the residual stress when integrating with different materials that involves many thin layers like GaN/AlGaN HEMT epi-layers.β-Ga2O3 is an emerging ultra-wide bandgap material showing promises for both power and RF devices. However, the material’s low thermal conductivity poses to be a challenge for efficient power delivery (at any frequencies). PC diamond was successfully grown on (‾¯201)β-Ga2O3 using proper nucleation technique and thermal characterizations were conducted. A thermal conductivity (diamond + nucleation) and thermal boundary resistance at the diamond/β-Ga2O3 interface of 110 ± 33 W/mK and 30.2 ± 1.8 m2K/GW, respectively were measured.Our current results demonstrates a very promising roadmap for wide bandgap semiconductors via diamond integration.

Effect of the Heat Dissipation System on Hard-Switching GaN-Based Power Converters for Energy Conversion

The design of a cooling system is critical in power converters based on wide-bandgap (WBG) semiconductors. The use of gallium nitride enhancement-mode high-electron-mobility transistors (GaN e-HEMTs) is particularly challenging due to their small size and high power capability. In this paper, we model, study and compare the different heat dissipation systems proposed for high power density GaN-based power converters. Two dissipation systems are analysed in detail: bottom-side dissipation using thermal vias and top-side dissipation using different thermal interface materials. The effectiveness of both dissipation techniques is analysed using MATLAB/Simulink and PLECS. Furthermore, the impact of the dissipation system on the parasitic elements of the converter is studied using advanced design systems (ADS). The experimental results of the GaN-based converters show the effectiveness of the analysed heat dissipation systems and how top-side cooled converters have the lowest parasitic inductance among the studied power converters.

Optimization of Thermal Design and Mold Flow Process for 3D SiP Structure

Abstract With the advent of the 5G era, major package and testing plants have been taking frequent action recently. Obviously, with higher and higher performance requirements, SiP is a functional package integrated multiple functional chips, including processor, memory into one package. However, thermal design is an important issue to be addressed at this time. This paper mainly presents a 3D SiP structure based on the combination of two substrates, integrating 4 components in a single package, total power consumption is 30 Watt. To address thermal management difficulties of this 3D SiP, a method is designed to increase the thermal path between the two boards. The Effects of the structure, number of via, and changing location of components aspects of the thermal performance are studied. The thermal vias was designed in between the two boards provide are direct heat dissipation, connecting the metal studs above passive components to improve thermal performance. Thermal performance with 240 vias is improved by 0.4%, while the number of vias increases from 240 to 912, the temperature decreases only 1.0%, 0.6% respectively. The difference of thermal resistance (θJB) comparison is 1.9%, 1.5% and 1.0%. There are limits to the improvement of vias, the effect of increasing the number of via is not as good as expected. However, increasing the thermal conduction path may have an effect on the void of mold flow. s 3D mold flow modeling of the transfer molding process with molded underfill (MUF) using Moldex3D is applied to optimize design and process parameters that can reduce device defects. There is one important challenge that faced air voids entrapment in molding area. Generally, the experiments involve a lot of design of experiment (DOE) matrixes which spend a lot of time to solve air void issue. As above reasons, the mold flow simulation can be used to apply molding parameters to find out optimum solutions for air void risk free of SiP, which can reduce development cycle time before mass production. From the mold flow simulation results, when the number of plunger segments increases and the tail flow rate decreases, the void issues can be effectively improved.

Thermal Design, Optimization, and Packaging of Planar Magnetic Components

This article is focused on the thermal design and three-dimensional (3-D) package optimization of planar magnetic components (PMCs), including transformers and inductors for application in an electric vehicle composite boost dc-dc converter. Each PMC comprises electrical windings in printed circuit board (PCB) form in combination with a ferrite core. Multiple features of each PMC package are thermally optimized for the proposed device configurations with given core size, core loss distribution, number of turns in the PCB winding, winding copper thickness, and winding loss distribution. These heuristically optimized features include a lower level cold plate structure with a conformal base for enhanced convective heat transfer, an upper level PMC cap structure for doubled-sided cooling through conductive heat flow to the cold plate, the implementation of functionally distributed copper thermal and electrothermal vias in the PCB winding for improved cross-plane thermal conductance, and judicious implementation of select materials at various locations and interfaces within the package. Detailed numerical modeling reveals the combined effect of this 3-D packaging strategy with a 79.3 °C and 48.5 °C maximum temperature reduction in the core and PCB winding, respectively, relative to a baseline device configuration. Select PMC experimental validation confirms the expected thermal performance of an optimized PCB design. The thermal design approach is relevant for a range of high-power-density electronics PMC packaging applications.

Thermal analysis of the design parameters of a QFN package soldered on a PCB using a simulation approach

Quad-Flat-No-Lead (QFN) packages are electric components that are producing a substantial amount of heat during operation due to significant power loss. Resulting elevated temperatures can lead to critical damage of the chip and the package, which could cause a loss of functionality. Therefore, controlling the maximum temperature within the package is crucial. Using thermal vias embedded in the PCB underneath the QFN is a common concept to support the heat flow. In this paper a simulation approach is presented using 3D Finite-Element-Modelling to identify the impact of influencing parameters on the temperature distribution within the package. Therefore, the build-up of the model is explained and applied material properties are given. Results for the determined temperature distribution for a reference parameter set are presented. Geometrical parameters like the thickness and the area size of the thermal pads and the copper layers are varied. Furthermore, the via count and distribution has been changed and additional inner layers have been added in order to act as a heat sink. The impact of these variations on the resulting component temperature will be discussed in the analysis part. The paper will round up with a discussion of simulation results and an outlook for future work.

Characterization of Highly Thermally Conductive Organic Substrates for a Double-Sided Cooled Power Module

Abstract Silicon-Carbide (SiC) power devices have become a promising option for traditional Silicon (Si) due to the superior material properties. To fully take advantage of the SiC devices, a high-performance power device packaging solution is necessary. This study proposes a cost-effective double-sided cooled (DSC) 1.2 kV SiC half-bridge power module using organic epoxy-resin composite dielectric (ERCD) substrates. The high mechanical and thermal performance of the power module is achieved by the low-modulus, moderate thermal conductivity, and relatively thin (120 μm) layer of ERCD material compared with traditional metal-clad ceramic approaches. This novel organic dielectric can withstand high voltage (5 kV @ 120 μm) and operate up to 250°C continuously, which is indispensable for high power applications. The thermal modeling results show that the equivalent thermal resistance junction-to-case (Rjc_eq) of the DSC power module using dual direct bonded copper (DBC) is 17% higher than the dual ERCD configuration. Furthermore, a non-insulated DSC power module concept is proposed for maximizing thermal performance by considering thermal vias in the ERCD substrate and direct-soldered heat sink. A thought process for optimization of thermal via design is demonstrated and it shows up to 24% of improvement on thermal performance compared with the insulated DSC power module.

Design and simulation of solutions to reduce the thermal resistance of lighting systems

The paper focuses on some essential steps in the development of high power line light. The research within the solved project deals with the development of a special extruded profile with a cooling channel and with heat removal by the circulation of the coolant and on the design of a cooling system with all the safety elements. The partial aim of the work is to determine the thermal resistance of individual parts of the device and to design modifications so that the total thermal resistance and maximum temperature are within the limits set by the effort to achieve maximum light output, but also the longevity, economy, safety, and reliability of operation. The analytical calculations, CFD simulations, and real testing were used to determine the required parameters. The main result presented in this paper is a novel developed PCB with a copper core and thermal vias.

Effects of Dummy Thermal Vias on Interconnect Delay and Power Dissipation of Very Large Scale Integration Circuits

The interconnect temperature of very large scale integration (VLSI) circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The thermal vias are regarded as a promising method to improve the temperature performance of VLSI circuits. In this paper, the extra thermal vias were used to decrease the delay and power dissipation of interconnect wires of VLSI circuits. Two analytical models were presented for interconnect temperature, delay and power dissipation with adding extra dummy thermal vias. The influence of the number of thermal vias on the delay and power dissipation of interconnect wires was analyzed and the optimal via separation distance was investigated. The experimental results show that the adding extra dummy thermal vias can reduce the interconnect average temperature, maximum temperature, delay and power dissipation. Moreover, this method is also suitable for clock signal wires with a large root mean square current.

Thermal management of the hotspots in 3-D integrated circuits

Vertical integration for microelectronics possesses significant challenges due to its fast dissipation of heat generated in multiple device planes. This paper focuses on thermal management of a 3-D integrated circuit, and micro-channel cooling is adopted to deal with the 3-D integrated circuitthermal problems. In addition, thermal through-silicon vias are also used to improve the capacity of heat trans-mission. It is found that combination of microchannel cooling and thermal through-silicon vias can remarkably alleviate the hotspots. The results presented in this paper are expected to aid in the development of thermal design guidelines for 3-D integrated circuits.

Power Semiconductor SMD Package Embedded in Multilayered Ceramic for Low Switching Loss

We propose a multilayered-substrate-based power semiconductor discrete device package for a low switching loss and high heat dissipation. To verify the proposed package, cost-effective, low-temperature co-fired ceramic, multilayered substrates are used. A bare die is attached to an embedded cavity of the multilayered substrate. Because the height of the pad on the top plane of the die and the signal line on the substrate are the same, the length of the bond wires can be shortened. A large number of thermal vias with a high thermal conductivity are embedded in the multilayered substrate to increase the heat dissipation rate of the package. The packaged silicon carbide Schottky barrier diode satisfies the reliability testing of a high-temperature storage life and temperature humidity bias. At 175 °C, the forward current is 7 A at a forward voltage of 1.13 V, and the reverse leakage current is below 100 μA up to a reverse voltage of 980 V. The measured maximum reverse current (IRM), reverse recovery time (Trr), and reverse recovery charge (Qrr) are 2.4 A, 16.6 ns, and 19.92 nC, respectively, at a reverse voltage of 300 V and di/dt equal to 300 A/μs.

Thermomechanical Stress-Aware Management for 3-D IC Designs

Thermal characteristics have been considered as one of the most challenging problems in 3-D integrated circuits (3-D ICs). Due to the thermal expansion coefficient mismatch between through-silicon vias (TSVs) and the silicon substrate, and the presence of elevated thermal gradients, thermomechanical stress issues are exacerbated in 3-D ICs. In this brief, we propose a solution that combines design-time and run-time techniques to reduce thermomechanical stress and the associated reliability issues. A TSV stress-aware floorplan policy is proposed to minimize the possibility of wafer cracking and interfacial delamination. In addition, a run-time thermal management scheme effectively eliminates large thermal gradients between layers. Experimental results show that the reliability of 3-D design can be significantly improved due to the reduced TSV thermal load and the elimination of mechanical damaging thermal cycling pattern. Moreover, impacts of thermal characteristics in TSVs and thermal vias insertion are explored.

End-to-End Analysis of Integration for Thermocouple-Based Sensors Into 3-D ICs

Solutions to the integration challenges of a new thermal sensor technology into 3-D integrated circuits (ICs) will be discussed in this paper. Our proposed architecture uses bimetallic thin-film thermocouples, which are thermally linked to points of measurement throughout the 3-D stack with dedicated vias. These vias will be similar to thermal through-silicon vias (TSVs) in structure, yet different in functionality. We propose a low-overhead design methodology by linking the sensor placement task with the existing thermal TSV planning phase for 3-D ICs. A fraction of thermal TSV resources is decoupled from their original use and repurposed for the temperature sensing infrastructure. Tradeoffs concerning the reduction of the thermal TSV resources are investigated. Furthermore, we present an end-to-end system, including the physical realization of the sensor network as well as its analog interface circuitry with the sensor data sampling unit. We demonstrate the operation and correctness of this interface with transistor-level simulations. Next, through thermal modeling and simulation using a state-of-the-art tool (FloTHERM), we demonstrate that we can achieve high accuracy (1 °C error) in temperature tracking while still maintaining the effectiveness of the thermal TSVs in heat management (conforming to a peak temperature constraint of 95 °C).

Heat transfer enhancement in MOSFET mounted on different FR4 substrates by thermal transient measurement**Project supported by the Collaborative Research in Engineering, Science & Technology (Grant No. P28C2-13).

Miniaturization of electronic package leads to high heat density and heat accumulation in electronics device, resulting in short life time and premature failure of the device. Junction temperature and thermal resistance are the critical parameters that determine the thermal management and reliability in electronics cooling. Metal oxide field effect transistor (MOSFET) is an important semiconductor device for light emitting diode-integrated circuit (LED IC) driver application, and thermal management in MOSFET is a major challenge. In this study, investigations on thermal performance of MOSFET are performed for evaluating the junction temperature and thermal resistance. Suitable modifications in FR4 substrates are proposed by introducing thermal vias and copper layer coating to improve the thermal performance of MOSFET. Experiments are conducted using thermal transient tester (T3ster) at 2.0 A input current and ambient temperature varying from 25°C to 75°C. The thermal parameters are measured for three proposed designs: FR4 with circular thermal vias, FR4 with single strip of copper layer and embedded vias, and FR4 with I-shaped copper layer, and compared with that of plain FR4 substrate. From the experimental results, FR4I–shaped shows promising results by 33.71% reduction in junction temperature and 54.19% reduction in thermal resistance. For elevated temperature, the relative increases in junction temperature and thermal resistance are lower for FR4I–shaped than those for other substrates considered. The introduction of thermal vias and copper layer plays a significant role in thermal performance.