Assembly of Large Flip Chip Die in Ceramic Packages

Abstract

Hermetic packaging is required to ensure the reliability of processors and application specific integrated circuit (ASIC) chips that are used in strategic systems, whose operating lifetimes typically exceed thirty years. Performance requirements for emerging system applications are dictating the need for one thousand or more I/O, which precludes the use of wire bonded devices. These packaging requirements can be met by flip chip bonding die onto multilayer, high temperature cofired ceramic substrates. The hermetic environment is provided by a Kovar metal ring that is brazed onto the ceramic and sealed in the final assembly step, by welding on a metal cover. Several process and design requirements must be met to achieve high reliability flip chip assemblies. Reflowed devices must be free of flux residues because they are corrosive, provide a path for ion diffusion, are a source of moisture and degrade the adhesion of underfill to chip and substrate. Removal of flux residues by cleaning is problematic because the gap between chip and substrate is very small relative to chip area. A better approach is to bond chips without flux, as we do, by reflowing them in a formic acid environment. An important reliability requirement for strategic hardware is the ability to sustain many cycles over extended temperature ranges. Temperature cycles induce plastic deformation in the solder connections as a result of stresses generated by the mismatch in thermal expansion coefficients of the chip and package. These stresses can be reduced significantly by underfilling the bonded chip with a filled adhesive. Choice of material as well as process execution impact the effectiveness of underfill enhancement of reliability. Optimization of both the physical design and composition of the solder connections is essential to producing reliable flip chip assemblies. We make extensive use of finite element analyses (FEA) in which we track the accumulation of plastic strain energy in the solder connections as they are subjected to temperature cycle induced stresses. Good correlations between the energy accumulated per cycle and the number of cycles to failure can be achieved if accurate state models of the solder are used. We have a catalog of Anand models for the solder compositions that we use in our FEA simulations. One of the more challenging aspects of designing high performance flip chip packages is matching the size and pitch of the bond pads on the ceramic with those on the chip. Current devices use 90 micron diameter pads on 200 micron pitch, but newer designs are migrating towards 80 micron diameter pads on 180 micron pitch. It challenging to maintain tight tolerances on pad geometries in these higher density packages and to route all the additional signals. Thermal management is also an important component of the package design. Thermal vias and thermally conductive underfills are used to remove heat from the front side of the chip. On the backside of the chip, the gap between chip and cover is minimized and filled with a high thermal conductivity interface material. High fidelity FEA modeling is necessary to ensure that the chip can be adequately cooled in its hermetic environment. This paper discusses the impact of these design and assembly factors on the reliability of high performance, hermetically packaged flip chip assemblies.