Large die flip chip packaging on organic substrates. the role of finite element analysis (FEA), materials characterization, failure analysis (FA) and test vehicles in development spins

Abstract

This work describes a case study where a process was developed focusing on four key factors that can be used to defme a methodology for packaging large die on high performance organic substrates: failure analysis (FA), f~te element analysis (FEA), test vehicle development and materials testing. The process consisted of in depth FA in the prototype phase to identify failure modes within typical thermomechanical stress tests such as air - to -air thermal cycling. Armed with a known failure mode, we desaihe the efforts to characterize a variety of assembly materials and utilize 3-D FEA of stress and warpage to determine optimal package construction. The use of low cost, quick turn test vehicles allowed us to verify the predicted optimal package and materials combinations through simple opens / shorts electrical tests during JEDEC reliability testing. Processability evaluations and optical coplanarity measurements allowed us to quickly select materials based on minimized warpage and optimum underfill characteristics. The result of this effort is a systematic approach to identify reliable large die flip chip packaging options for organic substrates in a cost effective, timely manner. 1. Iutrnductinn The use of failure analysis, materials testing, test vehicle development, and fmite element analysis (FEA) has been sbown to be indispensable at arriving at reliable packaging solutions. [l-31 Many researchers have used FEA as an important tool to evaluate package stresses and in some cases identify potential reliability limiting artifacts [4]. However, failure mode analysis is clearly the mnst important link to the usefulness of FEA as a tool for the packaging engineer. FEA alone cannot necessarily identify intrinsic weaknesses in a package design. Flip chip assemblies are complex systems containing elaborate geometries and material combinations. Beyond the obvious path of reducing the overall stress at interfaces and at other critical regions in a package, it is very difficult to identify the intrinsic weakness within the assembly until a failure occurs and methodical failure analysis identifies the root cause. Clearly, the need for inexpensive, readily available test assemblies to “mine sweep” potential failure modes in the presence of accelerated test conditions is required to perform product development at an acceptable pace, while keeping costs under control. FEA results will only be as good as the material property data provided. Due to the variety of measurement techniques and relative capabilities of materials vendors, the required material property data can he dfiicult to interpret correctly We present a case study where a failure mode was identified for a particular die size / body size combmation to enable a portion of OUT flip chip package portfolio. In order to accommodate the introduction of large SoC and high functionality die, the need to develop a packaging solution that extended this portfolio within the same substrate technology (as well as others) became apparent. The process by which this extension was made possible consisted of a systematic, four part knowledge based scheme using the tools mentioned above. We performed careful analysis of the existing failures followed by standardized materials characterization to enable the in depth FEA modeling required to understand the nature of the failure and to enable the extension of our package technology for large silicon. The use of carefully designed and inexpensive test vehicles, to perform evaluations at qualification stress conditions, allowed us to verify our model and to prove in an assembly process just ahead of product introduction.