Thermal Test Chip Research Articles

A novel steady-state method for measuring thermal conductivity of thermal interface materials with miniaturized thermal test chips

Thermal interface materials (TIMs) are widely used in electronic device packaging, and accurate characterization of their thermal properties is essential. However, existing TIM test platforms suffer from large size and inconsistency between copper-based test platforms and packaged silicon materials. To address these issues, this study proposes a method based on a miniaturized testing platform constructed using silicon-based thermal test chips (TTC). The thermal conductivity of several specimens was measured using steady-state heat source thermal transmission. The total thermal resistance, thermal contact resistance and thermal conductivity of several TIMs were evaluated through theoretical analysis and experimental verification. The thermal conductivity of several TIMs was tested using the proposed Back-to-Face and Back-to-Back TTC modules. The results demonstrate that this method exhibits high accuracy and can be used to characterize a wide range of TIMs.

Integrated manifold microchannels and near-junction cooling for enhanced thermal management in 3D heterogeneous packaging technology

The rapid advancement in electronic chip technology is driving the evolution of highly integrated and high-power configurations, which in turn imposes greater demands on thermal management. This study presents a novel approach to address the thermal management challenges associated with high-density integrated chips. By incorporating the near-junction cooling method into silicon-based chips, the thermal resistance during heat conduction is effectively reduced. To further enhance heat dissipation efficiency, we integrate manifold microchannels and near-junction cooling into an aluminum nitride ceramic substrate, creating a heterogeneous three-dimensional integrated chip. To verify the effectiveness of our approach, a thermal test chip and an aluminum nitride substrate with a manifold structure are meticulously prepared and packaged for experimental testing. Remarkably, the experimental results demonstrate that the heterogeneous integrated chip, featuring manifold microchannels, achieves an impressive heat dissipation capacity of 700 W/cm2 under normal operating temperature conditions. Additionally, sensitivity analysis and multi-objective optimization approach were employed, utilizing the Response Surface-Genetic Algorithm П(NSGAП), to optimize the manifold microchannels in the heterogeneous integrated chip. The optimization process yields significant improvements, reducing the total thermal resistance of the chip by 13.6 % and the maximum pressure drop by 68.5 %. These findings provide valuable theoretical insights and guidance for the thermal design of high heat flux integrated chips, and contribute to advance the design and development of high-performance integrated circuit systems.

Experimental study on the control of temperature oscillation in power electronics via pulsating jet impingement

Thermal oscillations in power electronics due to transient load conditions present a significant challenge. This experimental study investigates the application of intermittent jet impingement, coupled with transient heat flux boundary conditions of 100 W, 200 W, and 300 W, to a thermal test chip at a frequency of 0.5 Hz (70 % duty cycle), to assess its effectiveness in minimizing junction temperature fluctuations. Temperature oscillations were recorded to compare the advantages of intermittent pulsation over steady jet flow. The results demonstrate reduced hot spot temperature oscillations of 10 %, 12.5 %, and 16.7 % at 100 W, 200 W, and 300 W, respectively, at a Reynolds number of 8850. Remarkably, even during the pulsation off-period, the minimum temperature limit was maintained at the inlet temperature of the jet, attributed to the formation of strong vorticity rings at the end of the jet pulse, inducing a cooling effect and reducing the junction temperature. Pulsating jets exhibit superior control over temperature fluctuation compared to steady jets, with the reduction being more pronounced at Reynolds numbers closer to 2000 and diminishing as Reynolds number increases to 17000. Moreover, the heat transfer coefficient and the Nusselt number enhanced by 18 % due to pulsating jet impingement. An enhancement factor is introduced to quantify the benefits of using pulsating jets, revealing a higher reduction in temperature oscillation compared to steady jets at the same time-averaged Reynolds number, valid within the Reynolds number range of 2000–14000. Additionally, a correlation is proposed to calculate the enhancement factor for pulsating jets. Finally, the pulsating jet impingement proves to reduce the exergy destruction by 30 % compared to steady jet.

The effects of outlet size, shape, and location on spatial temperature distribution reduction via direct jet impinging in power electronics

Power electronics are used daily in a wide range of applications. Overheating is a major problem associated with power electronic chips. Direct jet impingement on silicon-based chips has emerged as a promising technique for power electronics cooling. However, this technique results in variations in spatial temperature between the center of the jet and the jet outlet location. This paper introduces a jet outlet design that facilitates a more uniform spatial temperature distribution. To this end, a numerical model is developed for a jet impingement configuration featuring four top circular outlets and experimentally validated using a thermal test chip with a jet Reynolds number of 7000. The resultant data show that reducing the outlet size by 30% results in a 31% decrease in the spatial temperature variance between the stagnation point and hot spot locations.Five outlet configurations are also investigated: eight circular top outlets; eight circular side outlets; four square top outlets; eight square top outlets; and eight square side outlets. Analysis of the temperature profiles of these designs reveals that the configuration featuring eight top circular outlets produces the highest spatial temperature difference, while the configuration featuring four top circular outlets (1.4 mm diameter) produces the smallest difference. Specifically, the four top circular outlet design enables a 42 % reduction in the spatial temperature difference, with a 3.8 % decrease in the pressure drop between the main inlet and outlet. Additionally, the findings show that this configuration produces a higher increase in the hot spot heat-transfer coefficient compared to the eight top circular outlet configuration (from 18,500 to 22,300 w/m2 °C, an increase of 20.5 %), thus flattening the spatial heat-transfer coefficient radially.

Experimental study of embedded manifold staggered pin-fin microchannel heat sink

High-heat-flux thermal management of high-power chips in electronic devices is becoming more and more critical. Manifold microchannel heat sink is one of the effective choices. In order to improve the heat dissipation capacity of manifold microchannel heat sink, a silicon-based thermal test chip including staggered pin-fin microchannels is designed and fabricated. Staggered pin-fin microchannels and rectangular microchannels with the same area size are embedded on the opposite side of the silicon-based thermal test chip for liquid-cooled heat dissipation. The experiments are conducted using HFE7100 as the working fluid. The heat transfer performance and the flow characteristic of two distinct microchannel structures are evaluated. It is found that the differences in temperature, convection heat transfer coefficient and pressure drop caused by different microchannel structures are greatly related to the mass flow rate. The heat transfer performance of the staggered pin-fin microchannel heat sink is better than that of the rectangular microchannel heat sink at a larger mass flow rate, but it also brings greater flow pressure drop. The bubble effect caused by the transition from single-phase to two-phase flow in microchannels makes the monotonicity of the convection heat transfer coefficient decrease significantly and the monotonicity of the pressure drop increase significantly. Compared to rectangular microchannel heat sinks, staggered pin-fin microchannel heat sinks reach the two-phase flow at higher heat flux. At the mass flow rate of 5 mL/s and the heat flux of 700 W/cm2, the staggered pin-fin microchannel heat sink can reduce the chip surface temperature by 8 K compared with the chip surface temperature of the rectangular microchannel heat sink.

Investigation on the unconstrained microfluidic heat sink with high anti-blockage capacity for multiple hotspots system

Microfluidic heat sinks are regarded as an efficient cooling solution in micro-electronic systems. However, as the hydraulic diameter of the microfluidic heat sinks shrinks, the blockage problem may occur due to the particles caused by cooling components? abrasion, which limits the application in long-term operation. This paper proposes an unconstrained microfluidic heat sink (UCMFHS) with high anti-blockage capacity for multiple hotspot systems, which aims to solve the block-age problem. The position and shape of the micro pin fins in UCMFHS are optimized by the CFD model. According to the test requirements of anti-blockage capacity and cooling performance, the test platform is built, which adopts the thermal test chips as heat source array. The results show that when the coolant particle concentration is 0.5%, the pressure drop variation is less than 0.3 kPa in UCMFHS, which is 99.43% lower than the control sample. The average temperature and temperature non-uniformity coefficient of 16 hotspots under the condition of 1200 W/cm2 and 125 mL per minute are 141.1? and 0.049, respectively. Therefore, the UCMFHS has both anti-blockage capacity and cooling capacity and is considered to have a high application prospect in long-term multi-hotspot cooling.

Investigation on the heat dissipation of high heat flux chip array by fractal microchannel networks

With the development of integrated circuits, high power, and high integration chip array devices are facing the requirements of high heat flux and temperature uniformity. The micro-channel heat sink can meet the heat dissipation requirements of chip array devices with high heat flux, and the flow channel with fractal structure can achieve high temperature uniformity of chip array. In this study, the H-shaped fractal micro-channel structure was proposed to cooling the 4?4 chip (1 ? 1 mm) array. The interior fillet structure was introduced to optimize T-shaped and L-shaped corner structures in the fractal channel. The simulation results show that the overall pressure drop of micro-channel heat sink with is reduced 18.7%, and the maximum temperature difference of 4?4 chip array is less than 1.2? at 1000 W/cm2. The micro-channel heat sink with interior fillet structure interior fillet structure was fabricated and assembled, and the hydro-thermal performance was characterized by thermal test chip at different flow rates and heat fluxes. The experimental results show that the standard deviation of temperature of 4?4 chip array is less than 3.5? at 1000 W/cm2 and 480 ml per minute. The error between experimental and simulation data is within ?1.5%, which proves the reasonability of CFD modelling and simulation. Furthermore, the results demonstrate that by introducing interior fillet structure into the T-shaped and L-shaped structures could reduce pumping power and improve temperature uniformity of chip array, which can be applied to improve the performance of the chip array devices with high heat flux.

Transient thermal measurement on nano-metallic sintered die-attach joints using a thermal test chip

The rapid development of power electronics has challenged the thermal integrity of semiconductor packaging. Further developments in this domain can be supported significantly by utilizing fast and flexible thermal characteristic evaluation. This study employs the transient dual interface method (TDIM) to characterize and compare the thermal resistance of Ag- and Cu-sintered die-attach joints using an in-house developed thermal test chip (TTC). The proposed TTC with 82.5% active area achieves a temperature sensitivity of 12 Ω/K and maximum power of 360 W per cell, which are 50% and 44% higher than the state-of-the-art, respectively. The uniformity of the temperature distribution (1 °C at 68 W) is verified by infrared thermography. The cost-effective manufacturing process allows the design to be applied to any substrate, such as SiC or GaN. Ag and Cu sintering is performed to bond the TTC on a Cu substrate, and the junction-to-case thermal resistance of the sintered structures is extracted. The lowest junction-to-case thermal resistance of 0.144 K/W is measured for the device sintered using Ag paste. Meanwhile, the Cu sintered structure exhibits a comparable value of 0.158 K/W. The proposed TTC in combination with TDIM accelerates the introduction of novel and cost-effective materials such as Cu.

Evaluation and Optimization of a Cross-Rib Micro-Channel Heat Sink.

This article presents a novel cross-rib micro-channel (MC-CR) heat sink to make fluid self-rotate. For a thermal test chip (TTC) with 100 w/cm2, the cross-ribs micro-channel were compared with the rectangular (MC-R) and horizontal rib micro-channel (MC-HR) heat sinks. The results show that, with the cross-rib micro-channel, the junction temperature of the thermal test chip was 336.49 K, and the pressure drop was 22 kPa. Compared with the rectangular and horizontal ribs heat sink, the cross-rib micro-channel had improvements of 28.6% and 14.3% in cooling capability, but the pressure drop increased by 10.7-fold and 5.5-fold, respectively. Then, the effects of the aspect ratio (λ) of micro-channel in different flow rates were studied. It was found that the aspect ratio and cooling performance were non-linear. To reduce the pressure drop, the inclination (α) and spacing (S) of the cross-ribs were optimized. When α = 30°, S = 0.1 mm, and λ = 4, the pressure drop was reduced from 22 kPa to 4.5 kPa. In addition, the heat dissipation performance of the rectangular, staggered fin (MC-SF), staggered rib (MC-SR) and cross-rib micro-channels were analyzed in the condition of the same pressure drop, MC-CR still has superior heat dissipation performance.

Experimental investigation of the embedded micro-channel manifold cooling for power chips

Power chips with high power dissipation and high heat flux have caused serious thermal management problems. Traditional indirect cooling technologies could not satisfy the increasing heat dissipation requirements. The embedded cooling directly inside the chip is the hot spot of the current research, which bears greater cooling potential comparatively, due to the shortened heat transfer path and decreased thermal resistance. In this study, the thermal behaviors of the power chips were demonstrated using a thermal test chip, which was etched with micro-channels on its substrate?s backside and bonded with a manifold which also fabricated with silicon wafer. The chip has normal thermal test function and embedded cooling function at the same time, and its size is 7 ? 7 ? 1.125 mm3. This paper mainly discussed the influence of width of micro-channels and the number of manifold channels on the thermal and hydraulic performance of the embedded cooling structure in the single-phase regime. Compared with the conventional straight micro-channel structure, the cooling coefficient of performance of the 8 ? ?50 (number of manifold distribution channels: 8, micro-channel width: 50 ?m) structure is 3.38 times higher. It is verified that the 8 ? ?50 structure is capable of removing power dissipation of 300 W (heat flux: 1200 W/cm2) at a maximum junction temperature of 69.6? with pressure drop of less than 90.8 kPa. This study is beneficial to promote the embedded cooling research, which could enable the further release of the power chips performance limited by the dissipated heat.

Design, integration and performance analysis of a lid-integral microchannel cooling module for high-power chip

In this paper, a lid-integral silicon-based microchannel cooling module (LSMCM) for a large-sized and high-power chip was designed, fabricated, and experimentally evaluated. The silicon-based microchannel heat sink was directly attached to a thermal test vehicle by high thermal conductive thermal interface material (TIM) and assembled with the molybdenum copper alloy (Mo70Cu) manifold. Finite volume method (FVM) simulations were conducted to optimize the channels in the slit and manifold. The non-uniformity of flow velocity is 8% when the flow rate is 1 L/min. The maximum temperature difference is 4.1 °C when the heat flux is 150 W/cm2 and the flow rate is 1 L/min. Based on the simulation results, the prototype of the module was fabricated. The top slit and bottom microchannel wafers were first fabricated by deep reactive ion etching (DRIE) and then bonded by wafer-to-wafer CuSn bonding to form the microchannel heat sink. SAC305 solder paste was used to seal the manifold and the microchannel heat sink. Last, a test facility was established to test the module’s pressure drop and heat dissipation performance. The test results showed that the pressure drop is 18.3 kPa when the flow rate is 1 L/min. The thermal resistance from chip to inlet coolant is 27.1 mm2K/W and the maximum temperature difference is 6.3 °C. The average temperature rise of the thermal test chip (TTC) is 52.9 °C when the total power reaches 1200 W. Therefore, LSMCM is expected to provide high heat removal ability and be used for large-sized and high-power chip.

Detection of Unusual Thermal Activities in a Semiconductor Chip Using Backside Infrared Thermal Imaging

Abstract Rapid detection of hardware Trojans on a semiconductor chip that may run malicious processes on the chip is a critical and ongoing security need. Several approaches have been investigated in the past for hardware Trojan detection, mostly based on changes in circuit parameters due to Trojan activity. Chip temperature is one such parameter that is closely related to the degree of Trojan activity. This paper carries out backside infrared (IR) imaging of a two-die three-dimensional integrated circuit (3D IC) thermal test chip in order to detect unusual thermal activities on the chip. Four distinct image processing algorithms are evaluated and compared in terms of speed, accuracy, and occurrence of false positives and negatives. The impact of background thermal activity and finite duration of Trojan activity on the accuracy of detection is investigated. Within the parameter space tested in this work, the histogram method is found to be the most effective at Trojan detection in the 3D IC. Modifications in data analysis techniques are proposed that improve Trojan detection performance. This work may help develop thermal imaging as a means for real-time Trojan detection and enhancement of security of modern semiconductor chips, including 3D ICs.

Experimental and Numerical Study of 3-D Printed Direct Jet Impingement Cooling for High-Power, Large Die Size Applications

In this article, we design, demonstrate, and characterize a 3-D printed package-level polymer jet impingement cooling solution on a 23×23 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> thermal test chip. The experimental hardware results for a nozzle pitch of 2 mm show that, with 1-kW power dissipation, at a coolant (deionized (DI) water) flow rate of 3 liters per minute (LPM), the measured average chip temperature increase is ~65 °C with a cooler pressure drop of 0.15 bar between the inlet and outlet connections. It is also shown that bare die cooling without lid [and thermal interface material (TIM)] shows better cooling performance than the lidded package. Second, an advanced 3-D printed manifold with an additional flow redistribution structure is demonstrated. The experimental results show that the improved design achieves a better chip temperature uniformity compared to the reference design, showing a reduction of the chip temperature gradient with a factor of 4 and 2.3 for a flow rate of 0.5 and 3 LPM, respectively, while no significant impact on the cooler pressure drop was measured. The numerical modeling studies predict an additional 15.4% thermal performance improvement, by reducing the nozzle pitch from 2 to 1 mm, for a flow rate of 3 LPM.

Microchannel Thermal Management System With Two-Phase Flow for Power Electronics Over 500 W/cm2 Heat Dissipation

In this article, a microchannel thermal management system (MTMS) with the two-phase flow using the refrigerant R1234yf with low global warming potential is presented. The thermal test vehicles (TTVs) were made of either single or multiple thermal test chips embedded in the substrates, which were then attached to the MTMS. The system included two identical aluminum microchannel heat sinks (MHSs) connected in series in the cooling loop, which also consisted of a gas flowmeter, a miniature compressor, a condenser, a throttling device, and accessory measurement components. The experimental results showed that the thermal management system could dissipate a heat flux of 526 W/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> while maintaining the junction temperature below 120 °C. For SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> with a higher junction temperature, e.g., 175 °C, the current system is expected to dissipate a heat flux as high as about 750 W/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The effects of the rotational speed of the compressor, the opening of the throttling device, TTV layout on MHS, and a downstream heater on the cooling performance of the system were analyzed in detail. The study shows that the present thermal management with a two-phase flow system is a promising cooling technology for the high heat flux SiC devices.

High porosity and light weight graphene foam heat sink and phase change material container for thermal management

During the last decade, graphene foam emerged as a promising high porosity 3-dimensional (3D) structure for various applications. More specifically, it has attracted significant interest as a solution for thermal management in electronics. In this study, we investigate the possibility to use such porous materials as a heat sink and a container for a phase change material (PCM). Graphene foam (GF) was produced using chemical vapor deposition (CVD) process and attached to a thermal test chip using sintered silver nanoparticles (Ag NPs). The thermal conductivity of the graphene foam reached 1.3 W m−1 K−1, while the addition of Ag as a graphene foam silver composite (GF/Ag) enhanced further its effective thermal conductivity by 54%. Comparatively to nickel foam, GF and GF/Ag showed lower junction temperatures thanks to higher effective thermal conductivity and a better contact. A finite element model was developed to simulate the fluid flow through the foam structure model and showed a positive and a non-negligible contributions of the secondary microchannel within the graphene foam. A ratio of 15 times was found between the convective heat flux within the primary and secondary microchannel. Our paper successfully demonstrates the possibility of using such 3D porous material as a PCM container and heat sink and highlight the advantage of using the carbon-based high porosity material to take advantage of its additional secondary porosity.

Experimental characterization and model validation of liquid jet impingement cooling using a high spatial resolution and programmable thermal test chip

High efficiency direct liquid jet impingement cooling with locally distributed outlets is very promising in high power electronic devices. In order to elucidate the flow-thermal interaction for micro-scale jet impingement cooling, sensitive temperature measurements with high spatial and temporal resolution are required. In this work, a programmable thermal test chip with 832 heater cells with 75% heater uniformity and 32 × 32 array of temperature sensors is introduced. The detailed measured temperature maps for different power dissipation patterns allow the in-depth study of the thermal performance of liquid jet impingement coolers and the detailed experimental validation of complex CFD models. The modeling and measurement study is applied to two jet impingement cooling implementations: (1) a single jet cooler with a 2 mm diameter nozzle, and (2) a multi-jet cooler with a 4 × 4 array of 500 µm inlet nozzles and distributed outlet nozzles. For both cooler configurations, the temperature measurements and CFD modeling results are investigated and compared for uniform and hot spot power dissipation patterns.

Location resolved transient thermal analysis to investigate crack growth in solder joints

Solder joint cracking is a common failure mechanism in microelectronic packages. To investigate interconnect integrity and reliability different inspections are established with their strengths and weaknesses: X-ray, scanning acoustic microscopy (SAM), Infrared (IR)-Thermal Imaging as well as Transient Thermal Analysis (TTA). TTA is well suited to detect changes in the thermal path, i.e. delamination in a package. However, spatial resolution in plane of an interconnection is restricted. Still, spatial resolution is necessary to analysis the crack growth in solder joints. In addition the local temperature strongly depends on the local position of a bad thermal contact. In the paper an innovative new test method, location resolved transient thermal analysis (LrTTA), is developed and its potential is investigated. LrTTA is based on transient thermal measurement (TTM). It uses several distinct diodes on a test chip to detect the thermal performance of interfaces and assemblies. The temperature is measured by the forward voltage as a function of time at different locations on the chip. Spatial resolution is obtained, e.g. cracks, voids and thickness variations can be resolved in the interface. For first experimental application of the method, a silicon thermal test chip with four differently located diodes was employed. The test chip was soldered onto an Aluminium Insulated Metal Substrate (Al-IMS) and exposed to temperature cycles. TTM were performed directly after assembly and after specific temperature shock cycle numbers (−40°C/+125°C). After data processing, the increase of the thermal impedance of each diode between the initial “0” cycles and “n” cycles was obtained. The thermal data are correlated with void formation detected by X-ray. Crack or delamination is in addition detected with scanning acoustic microscopy (SAM). As a quantitative analysis, a finite element (FE) model was set up and applied to analyze the solder joint with and without voids and also the crack propagation in the solder joint during temperature shock testing. Based on the FE modelling, the thermal influence of voids can be calculated and thus these voids can be detected. Further, based on the numerical analysis, crack size and location can be identified.

Si-Based Hybrid Microcooler With Multiple Drainage Microtrenches for High Heat Flux Cooling

Microfluid cooling solution is one of the most effective techniques for thermal management of high heat fluxes. A jet-based Si microcooler with multiple drainage microtrenches (MDMTs) has been developed for microelectronic thermal management. Integrated with MDMT in hybrid microcooler, the negative cross-flow effect between nearby nozzles is eliminated, and thus fully developed jet impingement can be enabled for each nozzle. An inlet/outlet flow arrangement layer has been introduced to achieve uniform pressure distribution. The effects of three types of arrangement structures on the hydraulic and thermal performance of microcooler have been analyzed and compared. Two different thermal/fluid simulation models have been constructed for microcooler design. The test vehicle with the new nozzle/trench layer is fabricated using double-side deep reactive-ion etching process. Assembly of the stacked microcooler and Si thermal test chip is finished through two-steps optimized thermal compression bonding process. With 0.05-W pumping power for the microcooler, the heat dissipation of 260 W/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> has been demonstrated, and the chip temperature can be maintained under 51 °C. Excellent agreement has been obtained between experimental and simulation results. With the MDMT, enhanced-microjet array impinging has been achieved, and uniform chip temperature distribution is obtained.

Investigations of Metal Systems in a Silicon Ceramic Composite Substrate for Electrical and Thermal Contacts as well as Associated Mounting Aspects

Abstract A quasi-monolithic silicon ceramic composite substrate (SiCer), allowing the advantageous combination of silicon MEMS technology with the LTCC technology represents a base substrate for new technology concepts. For the realization of such a substrate an adaptation (e. g. expansion coefficient) of the LTCC base material to silicon is required. Due to the fact that this TCE matched LTCC is not supplied with a metallization system, it is important to identify and evaluate suitable metal pastes. We present a compilation of evaluated silver- and gold-based metal pastes, as well as their characterization in terms of solderability and wire-bondability. With the use of thermal vias in combination with deep reactive ion etching to separate individual areas in the silicon layer [1], it is possible to adjust the thermal behavior of SiCer and of systems made of this substrate technology. Particularly for micro-electro-mechanical systems (MEMS) requiring high temperature gradients within the substrate material, e. g. radiation sensors, dew point sensors, energy harvesting or silicon heatsinks a silicon ceramic composite substrate in combination with thermal vias entails a high application potential. We investigate the thermal behavior of silicon ceramic composite substrates. Manufacturing technologies as well as measuring and simulation results regarding the use of thermal vias in SiCer are presented and discussed. Opportunities for construction and connection techniques for mounting a thermal test chip to SiCer are discussed. Furthermore, a simulation-based model to determine the heat dissipation behavior depending on number and arrangement of thermal vias is presented and compared with the measured values.

Design Optimization and Characterization of Silicon Microcooler System Through Finite-Element Modeling and Experimental Analyses

As chip power densities are now increasing beyond air cooling limits, a variety of liquid cooling methods are being investigated. The silicon microchannel cooling is an attractive approach due to its high heat transfer coefficient. In this paper, a thermal test chip with heating spots was mounted onto a synthetic diamond heat spreader, and then mounted onto the SMC cooler through the thermocompression bonding process. Finally, this structure was mounted onto the printed circuit board and connected with the manifold. The reliability of the cooler system was investigated through finite-element analysis (FEA) and characterization. Five types of FEA models were conducted considering process flow and application conditions, including shear test model, model of bonding the thermal chip to the heat spreader, model of the whole cooler system assembly, thermomechanical coupling analysis model considering hotspot heating, and temperature cycling reliability test model. Die attach materials were evaluated based on the shear test and modeling results. The cooler system was optimized based on the FEA results to reduce stress and warpage. The thermomechanical coupling simulation was conducted for the cooler system by considering nonuniform temperature distribution due to hotspots and cooling effect. The experimental results showed that the designed cooler system has good performance and reliability thermally and mechanically.