Integrated manifold microchannels and near-junction cooling for enhanced thermal management in 3D heterogeneous packaging technology

Abstract

The rapid advancement in electronic chip technology is driving the evolution of highly integrated and high-power configurations, which in turn imposes greater demands on thermal management. This study presents a novel approach to address the thermal management challenges associated with high-density integrated chips. By incorporating the near-junction cooling method into silicon-based chips, the thermal resistance during heat conduction is effectively reduced. To further enhance heat dissipation efficiency, we integrate manifold microchannels and near-junction cooling into an aluminum nitride ceramic substrate, creating a heterogeneous three-dimensional integrated chip. To verify the effectiveness of our approach, a thermal test chip and an aluminum nitride substrate with a manifold structure are meticulously prepared and packaged for experimental testing. Remarkably, the experimental results demonstrate that the heterogeneous integrated chip, featuring manifold microchannels, achieves an impressive heat dissipation capacity of 700 W/cm2 under normal operating temperature conditions. Additionally, sensitivity analysis and multi-objective optimization approach were employed, utilizing the Response Surface-Genetic Algorithm П(NSGAП), to optimize the manifold microchannels in the heterogeneous integrated chip. The optimization process yields significant improvements, reducing the total thermal resistance of the chip by 13.6 % and the maximum pressure drop by 68.5 %. These findings provide valuable theoretical insights and guidance for the thermal design of high heat flux integrated chips, and contribute to advance the design and development of high-performance integrated circuit systems.