TFT Structure Research Articles

高可靠性Cu BCE a-IGZO TFTs的制作

Back channel etched (BCE) amorphous InGaZnO (a-IGZO) can be fabricated with fewer photolithography masks and achieve smaller parasitic capacitance. However, the back channel of the BCE a-IGZO TFT is vulnerable to acid and plasma damage, which leads to problems of TFT uniformity and stability. In particular, with the introduction of gate driver on array (GOA) technology, it is increasingly urgent to improve the electrical uniformity and stability of TFTs. Therefore, it is an urgent requirement for technology and market to develop high reliability BCE IGZO TFTs. The electrical characteristic of the BCE configuration based a-IGZO TFTs were studied. The passivation layer, the selection of color filter material and design of GOA TFT structure were modified for lessening the influence of H2O molecules adsorbing on the back channel of the BCE-structure. The negative and positive bias temperature stress(N/PBTS) results revealed that the optimized GOA TFTs exhibited good device reliability-the Vth shift under gate voltage of -30 V at 80℃ is less than 1 V for 2 000 s. Finally, a high performance 215.9 mm(85 in) 8K4K 120 Hz GOA LCD was demonstrated.

Thermopower modulation clarification of the intrinsic effective mass in transparent oxide semiconductor BaSnO3

Although there are so many reports on the carrier effective mass (m*) of a transparent oxide semiconductor BaSnO3, it is almost impossible to know the intrinsic m* value because the reported m* values are scattered from 0.06 to 3.7 m0. Here we successfully clarified the intrinsic m* of BaSnO3, m*=0.40 0.01 m0, by the thermopower modulation clarification method. We also found the threshold of degenerate/non-degenerate semiconductor of BaSnO3; At the threshold, the thermopower value of both La-doped BaSnO3 and BaSnO3 TFT structure was 240 microvolt k-1, bulk carrier concentration was 1.4E19 cm-3, and two-dimensional sheet carrier concentration was 1.8E12 cm-2. When the EF locates above the parabolic shaped conduction band bottom, rather high mobility was observed. On the contrary, very low carrier mobility was observed when the EF lays below the threshold, most likely due to that the tail states suppress the carrier mobility. The present results are useful for further development of BaSnO3 based oxide electronics.

Investigation on the Gate Electrode Configuration of IGZO TFTs for Improved Channel Control and Suppression of Bias-Stress Induced Instability

The classic bottom-gate IGZO TFT structure requires a passivation layer application over the back-channel for stability and process integration. However, the passivation material deposition process usually degrades the interface quality and presents defect states at the back-channel interface which are difficult to compensate by a controlling gate electrode positioned on the opposite side of the semiconductor. A top-gate configuration takes advantage of a superior back-channel interface between the substrate and the sputtered IGZO film. The gate dielectric must be deposited on the IGZO which presents an inferior interface, however the influence of defect states can be reduced by annealing in an oxidizing ambient prior to the gate electrode deposition. As positioned directly above the inferior interface, there is an improvement in the ability of the gate potential to control the device operation in the presence of remaining defect states. This work presents an investigation on TFTs which have been fabricated with very similar process flows with the exception of the placement of the gate electrode. Bottom-gate TFTs with back-channel passivation that demonstrate good performance and resistance to aging have been realized, however bias-stress stability continues to remain a challenge. Top-gate TFTs have demonstrated improvement in the uniformity of device operation as well as bias-stress stability, and have the potential to offer an advantage in off-state performance (see fig. 1). Double-gate TFTs take further advantage of improved electrostatics, but present additional challenges in process integration. Results from all three gate electrode configurations will be compared. Device testing performed over a temperature range from 10 K to 400 K allows a comprehensive assessment of transport behavior (see fig. 2), with results used to refine a material and device model for TCAD simulation. Figure 1

Suppression of photo-bias induced instability for amorphous indium tungsten oxide thin film transistors with bi-layer structure

This study investigates the instability induced by bias temperature illumination stress (NBTIS) for an amorphous indium-tungsten-oxide thin film transistor (a-IWO TFT) with SiO2 backchannel passivation layer (BPL). It is found that this electrical degradation phenomenon can be attributed to the generation of defect states during the BPL process, which deteriorates the photo-bias stability of a-IWO TFTs. A method proposed by adding an oxygen-rich a-IWO thin film upon the a-IWO active channel layer could effectively suppress the plasma damage to channel layer during BPL deposition process. The bi-layer a-IWO TFT structure with an oxygen-rich back channel exhibits superior electrical reliability of device under NBTIS.

Analysis of Improved Performance Under Negative Bias Illumination Stress of Dual Gate Driving a- IGZO TFT by TCAD Simulation

We report the numerical simulation of the effect of a dual gate (DG) TFT structure operating under dual gate driving on improving negative bias illumination stress (NBIS) of amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs). With respect to the transfer characteristics of a-IGZO TFTs, we show a larger negative threshold voltage shift ( $\Delta V_{\mathrm {TH}})$ with increasing a-IGZO active layer thickness. This trend is confirmed by TCAD simulation, where the initial transfer curve is plotted under varying a-IGZO thickness keeping a constant density of states. Under varying a-IGZO thickness, TCAD simulation results confirm TFTs under DG driving shows significantly less $\Delta V_{\mathrm {TH}}$ shift under NBIS compared with that of single gate (SG) driving TFTs. Under 10 K seconds of NBIS, TCAD simulation results show the increase in donor-like states ( $N_{\mathrm {GD}})$ by $5.25 \times 10^{17}$ cm $^{\mathrm {-3}}$ eV $^{\mathrm {-1}}$ and acceptor-like states ( $N_{\mathrm {GA}})$ by $7.5\times 10^{16}$ cm $^{\mathrm {-3}}$ eV $^{\mathrm {-1}}$ .

Interpretation of Defect States in Sputtered IGZO Devices Using I-V and C-V Analysis

There has been significant progress in advancing the performance of IGZO TFTs; however device stability still remains a challenge. While traditional materials and techniques used for silicon-based TFTs may not be applicable, the influence of defect states can be reduced by annealing. The interpretation of non-ideal current-voltage (I-V) characteristics is not always unambiguous due to issues that may be related to carrier injection. Capacitance-voltage (C-V) analysis provides complementary information that is valuable in separating the influence of material and interface defects from other factors that influence transistor operation.In this work, bottom-gate, top-contact TFT structures and interdigitated capacitors fabricated using sputtered IGZO have been investigated. Interdigitated capacitors, unlike one-dimensional capacitors, are much more representative of the actual TFT structure; specifically the channel region. Annealing was performed at 300 - 400 °C in O2, N2and air ambient conditions. Silicon dioxide, aluminum oxide, and B-staged bisbenzocyclobutene-based (BCB) resins were applied as materials for back-channel passivation. Analytical measurements and both I-V and C-V results were used to refine a material model developed for TCAD device simulation [1]. The correlation between I-V and C-V characteristics will be presented.[1] T. C. Fung, C. S. Chuang, C. Chen, K. Abe, R. Cottle, M. Townsend, et al., "Two-dimensional numerical simulation of radio frequency sputter amorphous In-Ga-Zn-O thin-film transistors," Journal of Applied Physics, vol. 106, p. 084511, 2009.

33.2: A New Process and Structure for Oxide Semiconductor LCDs

AbstractA coplanar TFT structure has excellent characteristics in Δ Vp and channel length compared to conventional etch stopper TFT structure in AOS TFT LCD. In this paper, we introduce new 5 mask coplanar structure which reduces two mask steps compared to conventional 7 mask process. And we fabricated 4.5‐inch HD resolution panel in our R&D line with our new structure, and its transmittance is 12.5% improved by eliminating contact hole pattern.

10.4: Improvement of Stability on a‐IGZO LCD

AbstractWe have developed 10‐inch 300PPI and 65‐inch ultra high‐definition FFS LCD using amorphous In‐Ga‐Zn‐O(IGZO) TFT. After improvement of TFT's process and structure, the TFT performance is good enough for TFT‐LCD. In this report, we discuss our IGZO TFT process, uniformity and reliability.

Comparison of Electrical Properties and Bias Stability of Double-Gate a-HIZO TFTs According to TFT Structure

We fabricated two types of double-gate amorphous hafnium-indium-zinc oxide thin-film transistors: a back-channel etch (BCE) type and an etch stopper (ES) type. The normalized on-current and field-effect mobility of the BCE type are larger than those of the ES type. Furthermore, when applied with a positive bias stress, stability trends compared for each single-gate device are different according to structures. We suggest that the reason for the different electrical properties and bias stability originates from the ES structure in which some regions under the source/drain electrodes block the top-gate field; thus, there is no carrier accumulation or charge trapping into the dielectric layer.

Effect of enhanced-mobility current path on the mobility of AOS TFT

In this study, the mobility enhancement in an Amorphous Oxide Semiconductor Thin Film Transistor (AOS TFT), particularly the effect of enhanced-mobility current path was investigated. In the TFT structure, the a-IGZO single active channel layer was replaced by double layers. Indium Tin Oxide (ITO) was employed as an enhanced-mobility current path material and was embedded in an amorphous Indium Gallium Zinc Oxide (a-IGZO) channel layer of a conventional bottom gate structure TFT. To analyze the effect of the length of an additional current path, the a-IGZO channel length was fixed at 80μm, and the length of the ITO enhanced-mobility current path was increased to 20, 40, and 60μm. As a result, the mobility increased monotonically with the length of the enhanced-mobility current path and was predictable from the rule of mixture. The maximum saturation mobility of 28.3cm2/Vs resulted when the length of the enhanced-mobility current path was 60μm. This value is more than double that of a single path TFT. Such enhancement in mobility is attributed to the high conductivity of ITO and a good conduction band match between a-IGZO and ITO.

Analysis of Wet Etching Characteristics of a-IGZO Thin Film

Amorphous InGaZnO (a-IGZO) films are deposited on the glass substrate by RF sputtering and the influence of wet etching of a-IGZO films, etching rate, over etching features and TFT structure chose are investigated. The results show that Oxalic acid is best chose for IGZO film etching for side etching is about 0.1um , etching rate is 7.42 A/s which is easy to control and taper angle is acute. The traditional G-I-D type structure has been confirmed is not fit for the condition where the IGZO based TFT manufacture. G-D-I structure is tested and can be used in the TFT array manufacture.

Highly reliable oxide‐semiconductor TFT for AMOLED displays

Abstract— The stability and reliability of oxide‐semiconductor TFTs were investigated. The contact material to the oxide semiconductor affected the thermal stability of the TFT, and a molybdenum‐contact source/drain showed good stability. And the passivating film and TFT structure affected the stability against bias stress and humidity stress, and dc‐sputtered Al2O3 passivation and fully covered channel structure with an etching stopper or source/drain showed good reliability. Moreover, high photo‐stability was confirmed by the bias‐enhanced photo‐irradiation stress test. An 11.7‐in.‐diagonal qHD AMOLED display was demonstrated to provide an applicable solution for a large‐sized OLED and an ultra‐high‐definition LCD‐TV mass production.

69.2: Highly Reliable Oxide‐Semiconductor TFT for AM‐OLED Display

AbstractWe developed highly reliable oxide semiconductor TFT for AM‐ OLED displays. Passivating films, source/drain metals, and the TFT structure were optimized with an eye to improving device reliability to provide a lifetime over 10 years. An 11.7‐inch diagonal qHD AM‐OLED display was demonstrated to provide applicable solution for a large size OLED and an ultra‐high definition LCD TV mass‐production.

P‐33: Cu‐Mn Electrodes for a‐Si TFT and Its Electrical Characteristics

AbstractCu‐Mn alloy was used for electrode materials for amorphous Si TFT. The gate electrode showed a good adhesion to glass and low resistivity. The source/drain electrodes showed a good diffusion barrier property, Ohmic contact, and a low contact resistivity. TFT structure showed the ON/OFF ratio of better than 106.

42.4L: Late‐News Paper: 4 inch QVGA AMOLED Driven by the Threshold Voltage Controlled Amorphous GIZO (Ga2O3‐In2O3‐ZnO) TFT

AbstractWe successfully fabricated GIZO (Ga2O3‐In2O3‐ZnO) TFTs with high mobility of 2.6 cm2/Vs and threshold voltage standard deviation of 0.7V which is comparable to that of a‐Si TFTs. Because conventional 5 mask process and bottom gate TFT structure of back channel etch type with channel length of 5 μm is used, it is expected to be transferred to mass production line in near future. Also we report the dependency of threshold voltage on the post process after the back surface of GIZO is exposed and suggest the effective method for controlling the threshold voltage of amorphous GIZO TFTs. Finally we demonstrate 4 inch QVGA AMOLED display driven by GIZO TFTs.

P‐259L: Late‐News Poster: A 14inch Uniform AMOLED Display with Low Cost PECVD Based Microcrystalline Silicon TFT Backplanes

AbstractThis paper discusses development of uniform 14.1 inch AMOLED display using PECVD based microcrystalline silicon (mc‐Si) TFTs. Microcrystalline silicon was deposited using conventional 13.56 MHz Plasma Enhanced Chemical Vapor Deposition (PECVD) with novel gas precursors. The mc‐Si TFT's show a field effect mobility of around 1cm2/V.s and off‐current less than 1pA. Electrical stress on mc‐Si TFTs for a long time shows no significant threshold voltage shift indicating a stable TFT backplane. Significant uniformity improvements were made with novel TFT structure to give uniform AMOLED display. The deposition time for mc‐Si TFTs was significantly reduced by using a thin mc‐Si layer. Mc‐Si TFT backplanes using conventional PECVD equipment offers significant cost advantages over other competing laser and non‐laser polysilicon TFT technologies for AMOLEDs.

CONTROLLING INSTABILITIES OF HYDROGENERATED a-Si:H TFT UNDER BIAS TEMPERATURE STRESSING

The hydrogenerated amorphous silicon a-Si:H thin film transistors TFT with silicon nitride as a gate insulator have been stressed with independently varying gate (Vg), source (Vs), and gate-source (Vgs) bias voltage in order to elucidate the instability mechanism and suggest the new a-Si:H TFT structure. It was found that there was dependency of threshold voltage shift not only on Vgs, but also on Vg and Vs, which had not ever been reported. Its shift amount increased with increasing Vs and/or Vg. In this reports, we suggested the new TFT device structure to eliminate the dependency of Vth shift on Vg and Vs and found that with the new suggested TFT structure, the Vth shift controlling factor can only be Vgs.

Synthesis of InGaZnO4 Colloids and Its Application in a TFT Device

ABSTRACTThe deposition of amorphous InGaZnO4 (a-IGZO) semiconductor film, via a sputtering process, has been demonstrated in the literature. In this paper, we present a solution method as an alternative to obtain this semiconducting film. The dispersible IGZO colloids is formed first by co-precipitation of precursors, followed by hydrothermal treatment at 200°C for 1 hour and using CMC as the dispersion agent. The crystalline colloid would become amorphous when it was heated at above 250°C. The TFT structure was made by growing a dielectric silica layer using the CVD method, a metal layer using the sputtering method, and an active IGZO layer using the solution method. This device exhibits low operating voltage, the mobility is about 2cm2V−1s−1 and the Ion/Ioff ratio is 104. Further improvement in processing is needed.

A Novel Self-Aligned Etch-Stopper Structure With Lower Photo Leakage for AMLCD and Sensor Applications

In this letter, the authors introduce a novel self-aligned etch-stopper sidewall-contact hydrogenated amorphous silicon (a-Si : H) thin-film transistor (ESSC-TFT), which reduces the photo leakage current by more than one order of magnitude and increases the on-off ratio to seven orders of magnitude under back light illumination. Such a TFT will enable high-resolution and high-brightness liquid-crystal displays (LCDs) for next-generation TV, monitor, notebook, and mobile-phone applications. This ESSC-TFT design reduces the volume of a-Si film in which the active region can totally be shielded by the gate metal resulting in the prevention from direct back light illumination. With the sidewall contact, the hole current is reduced due to the smaller contact area between drain/source and a-Si layer. As well as the source, drain parasitic intrinsic resistance of a-Si can be also lessened by the ESSC-TFT structure. Although the defects between etched a-Si and n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+ </sup> a-Si film may degrade the on current, the ESSC-TFT still exhibits higher on-off ratio and lower leakage than the one in traditional etch-stopper (ES)-TFT structure. The ESSC-TFT structure can be used not only for TFT-LCD application but also for the applications that demand high on-off ratio and low-leakage device, such as X-ray image sensor

High Reliability and Performance Poly-Si TFTs for System in Displays

Narrow frame size IPS-mode LCD with high resolution system-in- display have been developed utilizing hybrid laser crystallization technology: SELAX are applied to low-power, high-speed circuits, and conventional ELC are used for the high- voltage circuits. The TFT degradation phenomena under dynamic stress are clarified, and the high-immunity TFT structure and high-quality gate insulator are proposed.