Testability Analysis Research Articles

Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design

A graph-based approach is presented for the generation of exact symbolic network functions in the form of rational polynomials of the complex frequency variable s for analog integrated circuits. The approach employs determinant decision diagrams (DDDs) to represent the determinant of a circuit matrix and its cofactors. A notion of multiroot DDDs is introduced, where each root represents a symbolic expression for an individual coefficient of the powers of s in the numerator and denominator of a network function, and multiple roots share their common subgraphs. A DDD-based algorithm is presented for generating s-expanded network functions. We prove theoretically and validate experimentally that the algorithm constructs in O(kl|DDD|) time an s-expanded DDD with no more than kl|DDD| vertices, where k is the degree of the denominator s polynomial, l is the maximum number of devices that connect to a circuit node, and |DDD| is the number of DDD vertices representing the circuit-matrix determinant. For a practical circuit, |DDD| is often many orders-of-magnitude less than the number of product terms. In contrast, previous approaches require the time and space complexities proportional to the number of product terms, which grows exponentially with the size of a circuit. Experimental results have demonstrated that the new approach can produce exact s-expanded-symbolic network functions for /spl mu/A741 operational amplifiers in several CPU seconds on an UltraSparc-I workstation. The expressive power of multiroot s-expanded DDDs is so remarkable that in one instance, over 10/sup 35/ symbolic product terms have been represented by a multiroot DDD with less than 17 K vertices. The compactness of DDDs is further demonstrated in the context of symbolic noise evaluation, where potentially many transfer functions, each being used for a noise source in the circuit, can be represented by a single DDD with the size comparable to that for a few transfer functions. This provides a powerful tool for solving many symbolic analysis problems such as deriving interpretable symbolic expressions, dominant pole/zero estimation, and analog testability analysis. We have also demonstrated that repetitive numerical evaluation with the derived s-expanded symbolic expressions for frequency-domain simulation and small-signal noise analysis can be much faster than SPICE-like simulators and the resulting expressions for a circuit block can be used as behavioral models for high-level simulation.

Improving Datapath Testability by Modifying Controller Specification

A digital circuit includes two main parts: a controller and a datapath. After connection of these two parts, both are subject to a sharp fall in testability due to the lack of controllability and observability at the interface. In this paper, we propose a method for specifying the control part in order to restore the testability of the datapath to a level close to the initial one, in other words its testability before connection. This testability driven specification affects the next state logic as well as the decoder part of the controller but does not make use of any scan‐based element. Based on the finite automata theory and on results of a testability analysis performed on the datapath, the proposed method entails very little area penalty.

Informed maintenance for next generation reusable launch systems

Perhaps the most substantial single obstacle to progress of space exploration and utilization of space for human benefit is the safety & reliability and the inherent cost of launching to, and returning from, space. The primary influence in the high costs of current launch systems (the same is true for commercial and military aircraft and most other reusable systems) is the operations, maintenance and infrastructure portion of the program's total life cycle costs. Reusable Launch Vehicle (RLV) maintenance and design have traditionally been two separate engineering disciplines with often conflicting objectives - maximizing ease of maintenance versus optimizing performance, size and cost. Testability analysis, an element of Informed Maintenance (IM), has been an ad hoc, manual effort, in which maintenance engineers attempt to identify an efficient method of troubleshooting for the given product, with little or no control over product design. Therefore, testability deficiencies in the design cannot be rectified. It is now widely recognized that IM must be engineered into the product at the design stage itself, so that an optimal compromise is achieved between system maintainability and performance. The elements of IM include testability analysis, diagnostics/prognostics, automated maintenance scheduling, automated logistics coordination, paperless documentation and data mining. IM derives its heritage from complimentary NASA science, space and aeronautic enterprises such as the on-board autonomous Remote Agent Architecture recently flown on NASA's Deep Space 1 Probe as well as commercial industries that employ quick turnaround operations. Commercial technologies and processes supporting NASA's IM initiatives include condition based maintenance technologies from Boeing's Commercial 777 Aircraft and Lockheed-Martin's F-22 Fighter, automotive computer diagnostics and autonomous controllers that enable 100,000 mile maintenance free operations, and locomotive monitoring system software. This paper will summarize NASA's long-term strategy, development, and implementation plans for Informed Maintenance for next generation RLVs. This will be done through a convergence into a single IM vision the work being performed throughout NASA, industry and academia. Additionally, a current status of IM development throughout NASA programs such as the Space Shuttle, X-33, X-34 and X-37 will be provided and will conclude with an overview of near-term work that is being initiated in FY00 to support NASA's 2 nd Generation Reusable Launch Vehicle Program.

Testing of core-based systems-on-a-chip

Available techniques for testing of core-based systems-on-a-chip (SOCs) do not provide a systematic means for synthesizing low-overhead test architectures and compact test solutions. In this paper, we provide a comprehensive framework that generates low-overhead compact test solutions for SOCs. First, we develop a common ground for addressing issues such as core test requirements, core access, and testing hardware additions. For this purpose, we introduce finite-state automata (FSA) for modeling tests, transparency modes, and testing hardware behavior. In many cases, the tests repeat a basic set of test actions for different test data that can again be modeled using FSA. While earlier work can derive a single symbolic test for a module in a register-transfer level (RTL) circuit as a finite-state automaton, this work extends the methodology to the system level and additionally contributes a satisfiability-based solution to the problem of applying a sequence of tests phased in time. This problem is known to be a bottleneck in testability analysis not only at the system level, but also at the RTL. Experimental results show that the system-level average area overhead for making SOCs testable with our method is only 4.5%, while achieving an average test application time reduction of 80% over recent approaches. At the same time, it provides 100% test coverage of the precomputed test sets/sequences of the embedded cores.

Cost/Quality Trade-off in Synthesis for BIST

This paper details our allocation for Built-in Self Test (BIST) technique used by the core part of our Testability Allocation and Control System (TACOS) called IDAT. IDAT tool objective is to fulfill the designer requirements regarding selected design and testability attributes of a circuit data-path to be synthesized. A related tool is used to synthesize a test controller for the final testable circuit. The allocation process of BIST resources in the data-path is driven by two trade-off techniques performed in order to: (1) at the local level, select the optimal set of Functional Units (FUs) to be BISTed, using a new testability analysis method and (2) at the global level, for each selected FU of this set, choose either to allocate its BIST version (when available in a library) or to connect it to an internal Test Pattern Generator (TPG) and Test Results Checker (TRC). When necessary, a last step of the process is the allocation of scan chains used to test the remaining untested interconnections. Experiments show the results of our allocation for BIST technique on three benchmarks.

Fault simulation and modelling of microelectromechanical systems

High-reliability and safety-critical markets for microelectromechanical systems are driving new proposals for the integration of efficient built-in test and monitoring functions. The realisation of this technology will require support tools and validation methodologies including fault simulation and testability analysis and full closed-loop simulation techniques to ensure cost and quality targets. This article proposes methods to extend the capabilities of mixed signal and analogue integrated circuit fault simulation techniques to MEMS by including failure mode and effect analysis data and using behavioural modelling techniques compatible with electrical simulators.

Partial Scan Methodologies-A Survey

In the paper the survey of partial scan methodologies is presented. Existing approaches for selecting FFs for partial scan can be classified as testability analysis based, test generation based and structural analysis based. In the paper, the results of our research activities are described as well. The methodology is based on such concepts as Test Input Register (TIR), Test Driver (TDR), Test Receiver (TRV), Test Output Register (TOR) and Test Transmitter (TTR).

TAIR: testability analysis by implication reasoning

To predict the difficulty of testing a wire stuck-at fault, testability analysis algorithms provide an estimated testability value by computing controllability and observability. In most common previous work such as COP and SCOAP, signal correlation between controllability and observability is not well handled. As a result, the estimated values can be quite inaccurate, On the other hand, some previous work can take into account signal correlation but may require more CPU time. This paper discusses an efficient method for testability analysis improvement. Our algorithm starts with results obtained from conventional testability analysis such as COP. For each stuck- at fault, we gradually refine these results by recursively applying some simple signal correlation rules. Experimental results show that, with reasonable run-time overhead, significant improvement for testability analysis can be achieved.

TAO-BIST: A framework for testability analysis and optimization for built-in self-test of RTL circuits

In this paper, we present TAO-BIST, a framework for testing register-transfer level (RTL) controller-datapath circuits using built-in self-test (BIST). Conventional BIST techniques at the RTL generally introduce more testability hardware than is necessary thereby causing unnecessary area, delay and power overheads. They have typically been applied to only application-specific integrated circuits (ASICs). TAO-BIST adopts a three-phased approach to provide an efficient BIST framework at the RTL. In the first phase, we identify and add an initial set of test enhancements to the given circuit. In the second phase, we use regular-expression based high-level symbolic testability analysis of a BIST model of the circuit to completely encapsulate justification/propagation information for the modules under test. The regular expressions so obtained are then used to construct a Boolean function in the final phase for determining a test enhancement solution that meets delay constraints with minimal area overheads. Our method is applicable to a wide spectrum of circuits including ASICs, application-specific programmable processors (ASPPs), application-specific instruction processors (ASIPs), digital signal processors (DSPs), and microprocessors. Experimental results on a number of benchmark circuits show that high fault coverage (>99%) can be obtained with our scheme. The average area and delay overheads due to TAO-BIST are only 6.0% and 1.5%, respectively, for a bit-width of 16. These overheads decrease further with an increase in bit-width. The test application time to achieve the high fault coverage for the whole controller-datapath circuit is also quite low.

A BIST scheme for RTL circuits based on symbolic testability analysis

This paper introduces a novel scheme for testing register-transfer level (RTL) controller/data paths using built-in self-test (BIST). The scheme uses the controller netlist and the data path of a circuit to extract a test control/data flow (TCDF) graph. This TCDF is used to derive a set of symbolic justification and propagation paths (known as the test environment) to test some of the operations and variables present in it. If it becomes difficult to generate such test environments with the derived TCDF's, a few test multiplexers are added at suitable points in the circuit to increase its controllability and observability. The test environment of an operation (variable) guarantees the existence of a path from the primary inputs of the circuit to the inputs of the module (register) to which the operation (variable) is mapped, and a path from the output of the module (register) to a primary output of the circuit. Since the search for a test environment is done symbolically, it is very fast and needs to be done only once for each module or register,in the circuit. This test environment can then be used to exercise a module or register in the circuit with pseudorandom pattern generators which are placed only at the primary inputs of the circuit. The test responses can he analyzed with signature analyzers which are only placed at the primary outputs of the circuit. Unlike many RTL BIST schemes, an increase in the data path bit-width does not adversely impact the complexity of our testability analysis scheme since the analysis is symbolic. Every module in the module library is made random-pattern testable, whenever possible, using gate-level testability insertion techniques. This is a one-time cost. Finally, a BIST controller is synthesized to provide the necessary control signals to form the different test environments during testing, and a BIST architecture is superimposed on the circuit. Experimental results on a number of industrial and university benchmarks show that high fault coverage (>99%) can be obtained with our scheme. The average area overhead of the scheme is 6.9% which is much lower than many existing logic-level BIST schemes. The average delay overhead is only 2.5%. The test application time to achieve the high fault coverage for the whole circuit is also quite low.

Using robust adaptive mixing for statistical fault macromodelling

The design and analysis of analogue circuits can be speeded up if accurate macromodels are used in place of full, transistor-level netlists. Similarly, testability analysis of analogue circuits at the transistor level is difficult because of the large CPU times needed for fault simulation. Macromodelling circuits under catastrophic fault conditions is difficult because the faulty behaviour is not easily predicted. Moreover, the variances in faulty behaviour, because of parametric tolerances, are not the same as the variance of the fault free behaviour. An algorithm is presented for statistical fault macromodelling of analogue circuits. The circuit macros are modelled using a robust adaptive mixing algorithm, which is based on mutual information theory and robust statistical methods. The experimental results show that the CPU time required for statistical fault macromodelling is very small and the model accuracy is very high.

Comments on "Linear circuit fault diagnosis using neuromorphic analyzers"

For the original paper see ibid., vol. 44, no. 3, p. 188-96 (1997). In the aforementioned paper, Spina and Upadhyaya presented a method for the fault diagnosis of analog linear circuits. The method, which is based on a white noise generator and an artificial neural network for response analysis, has been applied to circuits of reasonable dimensions, taking into account the effect of the component tolerances. However, the commenters state that the proposed method does not take into account the testability analysis of the circuit under test. They point out that research on testability analysis of linear circuits has been developed by several authors in the last 20 years, and algorithms and programs for testability evaluation have been presented in several publications. It is their opinion that the testability analysis concept could be useful in the approach proposed by Spina and Upadhyaya to improve the quality of the results even further. Here they discuss this possibility.

Hierarchical test generation and design for testability methods for ASPPs and ASIPs

In this paper, we present design for testability (DFT) and hierarchical test generation techniques for facilitating the testing of application-specific programmable processors (ASPPs) and application-specific instruction processors (ASIPs). The method utilizes the register-transfer level (RTL) circuit description of an ASPP or ASIP to come up with a set of test microcode patterns which can be written into the instruction read-only memory (ROM) of the processor. These lines of microcode dictate a new control/data flow in the circuit and can be used to test modules which are not easily testable. The new control/data flow is used to justify precomputed test sets of a module from the system primary inputs to the module inputs and propagate output responses from the module output to the system primary outputs. The testability analysis, which is based on the relevant control/data flow extracted from the RTL circuit, is symbolic. Thus, it is independent of the bit-width of the data path and is extremely fast. The test microcode patterns are a by-product of this analysis. If the derived test microcode cannot test all untested modules in the circuit, then test multiplexers are added (usually to the off-critical paths of the data path) to test these modules. This is done to guarantee the testability of all modules in the circuit. If the control microcode memory of the processor is erasable, then the test microcode lines can be erased once the testing of the chip is over. In that case, the DFT scheme has very little overhead (typically less than 1%). Otherwise, the test microcode lines remain as an overhead in the control memory. The method requires the addition of only one external test pin. Application of this technique to several examples has resulted in a very high fault coverage (above 99.6%) for all of them. The test generation time is about three orders of magnitude smaller compared to an efficient gate-level sequential test generator. The average area overhead (without assuming an erasable ROM) is 3.1% while the delay overheads are negligible. This method does not require any scan in the controller or data path. It is also amenable to at-speed testing.

A functional-level testability measure for register-level circuits and its estimation

Estimation of circuit testability is an important issue when evaluating the circuit design. A testability measure indicates how easy or difficult it would be to generate tests for the circuit. STAFAN (Statistical Fault Analysis) is a well known gate-level testability analysis program which predicts the fault coverage of a digital circuit under the stuck-at fault model, without actually performing fault simulation. STAFAN offers speed advantage over other testability analysis programs such as SCOAP; further, it explicitly predicts the fault coverage for a given test set, unlike other testability measures which are harder to interpret. We show how a STAFAN-like testability analysis program can be constructed for circuits built out of register-level modules such as adders, multipliers, multiplexers, and busses. Our tool, which we call FSTAFAN, is useful in a testability-driven high-level synthesis environment. We have implemented FSTAFAN on a Sun/SPARC workstation and describe its performance on some register-level circuits.

Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST

This paper proposes a new testability analysis and test-point insertion method at the register transfer level (RTL), assuming a full scan and a pseudorandom built-in self-test design environment. The method is based on analyzing the RTL synchronous specification in synthesizable very high speed integrated circuit hardware descriptive language (VHDL). A VHDL intermediate form representation is first obtained from the VHDL specification and then converted to a directed acyclic graph (DAG) that represents all data dependencies and flow of control in the VHDL specification. Testability measures (TMs) are computed on this graph. The considered TMs are controllability and observability for each bit of each signal/variable that is declared or may be implied in the VHDL specification. Internal signals of functional modules (FMs) such as adders and comparators are also analyzed to compute their controllability and observability values. The internal signals are obtained by decomposing at the RTL large FMs into smaller ones. The calculation of TMs is carried out at a functional level rather than the gate level, to reduce or eliminate errors introduced by ignoring reconvergent fanouts in the gate network, and to reduce the complexity of the DAG construction. Based on the controllability/observability values, test-point insertion is performed to improve the testability for each bit of each signal/variable. This insertion is carried out in the original VHDL specification and thus becomes a part of it unlike in other existing methods. This allows full application of RTL synthesis optimization on both the functional and the test logic concurrently within the designer constraints such as area and delay. A number of benchmark circuits were used to show the applicability and the effectiveness of our method in terms of the resulting testability, area, and delay.

A low overhead design for testability and test generation technique for core-based systems-on-a-chip

In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has several advantages in terms of time-to-market and system cost, testing such core-based systems is difficult, mainly due to the problem of justifying test sequences at the inputs of a core embedded deep in the circuit and propagating test responses from the core outputs. In this paper, we first present a design for testability technique for testing such core-based systems. In this scheme, untestable cores are first made testable using hierarchical testability analysis techniques. If necessary, additional testability hardware is added to the cores to make them transparent so that they can propagate test data without information loss. This testability and transparency technique is currently applicable to cores of the following types: application-specific integrated circuits, application-specific programmable processors, and application-specific instruction processors. Other core types can be made testable and transparent using traditional techniques. The testable and transparent cores can then he integrated together with some system-level testability hardware to ensure justification of precomputed test sequences of each core from system primary inputs to the core inputs and propagation of test responses from core outputs to system primary outputs. Justification and propagation of test sequences are done at the system level by extending and suitably modifying the symbolic hierarchical testability analysis method that has been successfully applied to register-transfer level circuits. Since the testability analysis method is symbolic, the system test generation method is independent of the bit-width of the cores. The system-level test set is obtained as a byproduct of the testability analysis and insertion method without further search. The test methodology was applied to six example systems. Besides the proposed test method, the two methods that are currently used in the industry were also evaluated: (1) FScan-BScan, where each core is full-scanned, and system test is performed using boundary scan and (2) FScan-TBus, where each core is full-scanned, and system test is performed using a test bus. The experiments show that the proposed scheme has significantly lower area overhead, delay overhead, and test application time compared to FScan-BScan and FScan-TBus, without any compromise in the system fault coverage.

Incremental Testability Analysis for Partial Scan Selection and Design Transformations

This paper presents an efficient estimation method for incremental testability analysis, which is based partially on explicit testability re-calculation and partially on gradient techniques. The analysis results have been used successfully to guide design transformations and partial scan selection. Experimental results on a variety of benchmarks show that the quality of our incremental testability analysis is similar to those of the conventional explicit testability re-calculation methods and the technique can be used efficiently for improving the testability of a design during the high-level test synthesis and partial scan selection processes.

Testability analysis and behavioral testing of the Hopfield neural paradigm

Testability analysis and test pattern generation for neural architectures can be performed at a very high abstraction level on the computational paradigm. In this paper, we consider the case of Hopfield's networks, as the simplest example of networks with feedback loops. A behavioral error model based on finite-state machines (FSM's) is introduced. Conditions for controllability, observability and global testability are derived to verify errors excitation and propagation to outputs. The proposed behavioral test pattern generator creates the minimum length test sequence for any digital implementation.

SCOAP‐based Testability Analysis from Hierarchical Netlists

Circuits of VLSI complexity are designed using modules such as adders, multipliers, register files, memories, multiplexers, and busses. During the high‐level design of such a circuit, it is important to be able to consider several alternative designs and compare them on counts of area, performance, and testability. While tools exist for area and delay estimation of module‐level circuits, most of the testability analysis tools work on gate‐level descriptions of the circuit. Thus an expensive operation of flattening the circuit becomes necessary to carry out testability analysis. In this paper, we describe a time and space‐efficient technique for evaluating the well known SCOAP testability measure of a circuit from its hierarchical description with two or more levels of hierarchy. We introduce the notion of SCOAP Expression Diagrams for functional modules, which can be precomputed and stored as part of the module data base. Our hierarchical testability analysis program, HISCOAP, reads the SCOAP expression diagrams for the modules used in the circuit, and evaluates the SCOAP measure in a systematic manner. The program has been implemented on a Sun/SPARC workstation, and we present results on several benchmark circuits, both combinational and sequential. We show that our algorithm also has a straightforward parallel realization.

A novel approach to random pattern testing of sequential circuits

Random pattern testing methods are known to result in poor fault coverage for most sequential circuits unless costly circuit modifications are made. In this paper, we propose a novel approach to improve the random pattern testability of sequential circuits. We introduce the concept of holding signals at primary inputs and scan flipflops of a partially scanned sequential circuit for a certain length of time, instead of applying a new random vector at each clock cycle. When a random vector is held at the primary inputs of the circuit under test or at the scan flip-flops, the system clock is applied and the primary outputs of the circuit are observed. Information obtained from a testability analysis or test generator is used to determine the number of clock cycles for which each random vector is to be held constant. The method is low cost and the results of our experiment on the benchmark circuits show that it is very effective in providing fault coverage close to the maximum obtainable fault coverage using random patterns with full scan.